8 October 1996 High-speed systolic architectures for median-type filtering
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Abstract
A new efficient parallel algorithm and an architecture for order statistic, weighted order statistic and stack filters are suggested in this paper. This design is based on coding the order relations between input samples within the filter's window by so called binary ordering P-matrices. A simple scheme utilized in the design allows to update the current binary matrix from the previous one using just one parallel step of comparisons and simple, regular bit shifts. The architecture of the design is simple and suits well for implementation in systolic arrays. It is unified for all the above filters meaning that in all the cases the structure is the same and only one block, the output former, is different for each of these filters.
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Jaakko T. Astola, David Zaven Gevorkian, "High-speed systolic architectures for median-type filtering", Proc. SPIE 2823, Statistical and Stochastic Methods for Image Processing, (8 October 1996); doi: 10.1117/12.253461; https://doi.org/10.1117/12.253461
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KEYWORDS
Digital filtering

Binary data

Electronic filtering

Filtering (signal processing)

Matrices

Multiplexers

Linear filtering

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