22 October 1996 Embedded-processor architecture for parallel DSP algorithms
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A methodology for constructing parallel embedded DSP systems is described. The method uses a software and embedded processor abstraction to help raise the level of problem analysis above the raw state machine concept. Custom architectures are constructed by using multiple copies of a core embedded processor linked together with FIFO memories or other communication structures, and augmented with appropriate high speed data manipulation IO devices. Some field programmability and customization is possible through the use of SRAM program memories.
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Rick F. Hobson, Rick F. Hobson, Peter S. Wong, Peter S. Wong, S. A. Evenson, S. A. Evenson, } "Embedded-processor architecture for parallel DSP algorithms", Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); doi: 10.1117/12.255463; https://doi.org/10.1117/12.255463

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