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22 October 1996 Folding large regular computational graphs onto smaller processor arrays
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Index Mapping is a novel approach to mapping a class of algorithms onto linear permutation networks such as the shuffle graph. This class includes the Viterbi Algorithm, the Fast Fourier Transform, and the Bitonic Sort, among others. With this technique, it is possible to analyze a large number of possible partitioning and scheduling schemes and choose for a given technology the optimum implementation. This technique will be demonstrated by two mappings of a variable and large constraint length Viterbi decoder onto a smaller fixed interconnection processing network with minimum hardware resources. The hardware built for this mapping can calculate the Viterbi algorithm for any constraint length from 3 to 15 with programmable code polynomials and code rates from 1/2 to 1/6.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kevin J. Page and Paul M. Chau "Folding large regular computational graphs onto smaller processor arrays", Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996);


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