Folding large regular computational graphs onto smaller processor arrays

Kevin J. Page; Paul M. Chau

doi:10.1117/12.255453

Translator Disclaimer

22 October 1996 Folding large regular computational graphs onto smaller processor arrays

Kevin J. Page; Paul M. Chau

Author Affiliations +

Proceedings Volume 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI; (1996) https://doi.org/10.1117/12.255453
Event: SPIE's 1996 International Symposium on Optical Science, Engineering, and Instrumentation, 1996, Denver, CO, United States

Abstract

Index Mapping is a novel approach to mapping a class of algorithms onto linear permutation networks such as the shuffle graph. This class includes the Viterbi Algorithm, the Fast Fourier Transform, and the Bitonic Sort, among others. With this technique, it is possible to analyze a large number of possible partitioning and scheduling schemes and choose for a given technology the optimum implementation. This technique will be demonstrated by two mappings of a variable and large constraint length Viterbi decoder onto a smaller fixed interconnection processing network with minimum hardware resources. The hardware built for this mapping can calculate the Viterbi algorithm for any constraint length from 3 to 15 with programmable code polynomials and code rates from 1/2 to 1/6.

Citation Download Citation

Kevin J. Page and Paul M. Chau "Folding large regular computational graphs onto smaller processor arrays", Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); https://doi.org/10.1117/12.255453

ACCESS THE FULL ARTICLE