Variation is playing an increasingly important role in microelectronics manufacturing; variation not only impacts yield but also limits performance and reliability. Statistical metrology is an emerging body of methods for the systematic characterization and study of variation in semiconductor manufacturing. This paper considers the key elements of statistical metrology and reviews current progress in these areas, including (1) measurement methods and data gathering, (2) variation modeling and data analysis, and (3) study of the impact of variation. Potential applications of the methodology are widespread, with significant existing work in equipment characterization, layout optimization, and circuit impact analysis. Statistical metrology is an exciting new area of research that will play a critical role in future design and manufacture practice.

A methodology has been developed as part of a statistical metrology framework (1) to assess the relative range and distribution of intra-die, or die-level, polysilicon critical dimension variation as opposed to wafer-level, or inter-die, poly-CD variation; (2) to identify the key layout factors involved in poly-CD intra-die variation; and (3) to develop first-order semi-empirical models for poly-CD variation. A new approach utilizing multivariate analysis of variance methods is described to model the die- and wafer- level variation components. We show that pattern dependent variation is approximately twice as large as wafer-level variation. In addition, we find that spatial position plays a strong role: the first-order pattern dependent variation model (or die 'signature') shows a strong dependence on spatial position across the wafer, and individual components of the model demonstrate different spatial position sensitivities.

Poor control of wire geometry can result in unacceptable variations in signal propagation velocity and cross-talk. A novel laser diffraction technique for the real-time determination of global interconnect metrology is presented and tested on several different types of chips. Analysis of the diffraction patterns produced by He-Cd (lambda equals 442 nm) and He-Ne (lambda equals 633 nm) laser irradiation of the interconnect structure is shown to reveal global information on variations in wiring parameters. The diffraction intensity profile for a commercial microprocessor fabricated using 2 micrometer design rules is used to test the validity of the approach. Standard diffraction theory reveals that the process variation in wire pitch is of the order of 9%, a value confirmed by examination under a phase contrast microscope. In addition to wire pitch variations the diffraction technique is also used for the measurement of the characteristic fractal dimension of the wiring. Initial results indicate that these measurements may provide an extremely rapid method of assessing important wiring figures of merit, such as the on- chip Rent exponent.

At Motorola's MOS-12 facility automated measurements on 200- mm diameter wafers proceed in a hands-off 'load-and-go' mode requiring only wafer loading, measurement recipe loading, and a 'run' command for processing. Upon completion of all sample measurements, the data is uploaded to the factory's data collection software system via a SECS II interface, eliminating the requirement of manual data entry. The scope of in-line measurement automation has been extended to the entire metrology scheme from job file generation to measurement and data collection. Data analysis and comparison to part specification limits is also carried out automatically. Successful integration of automated metrology into the factory measurement system requires that automated functions, such as autofocus and pattern recognition algorithms, display a high degree of reliability. In the 24- hour factory reliability data can be collected automatically on every part measured. This reliability data is then uploaded to the factory data collection software system at the same time as the measurement data. Analysis of the metrology reliability data permits improvements to be made as needed, and provides an accurate accounting of automation reliability. This reliability data has so far been collected for the CD-SEM (critical dimension scanning electron microscope) metrology tool, and examples are presented. This analysis method can be applied to such automated in-line measurements as CD, overlay, particle and film thickness measurements.

This paper presents a new method to isolate process steps causing performance spread of analogue or digital circuits. It is based on the analysis of process control or device parameters, sampled over one or more wafers of one or more lots. The analysis includes a physical approach of the parameters combined with a correlation coefficient study. This methodology which links parameters to process quantities, results in short-loop processing as well as in enhanced yield improvement.

To improve accuracy of defect densities, yield prediction and failure analysis, this paper compares data on defects and faults collected by electrical measurement methods and laser scattering systems. For that we choose the checkerboard test structure design to partition the whole chip area into a large number of subchips, each containing defect sensitive comb lines. A digital tester based measurement procedure enables the detection and separation of faults. Additional analysis procedures guarantee a layer- specific fault localization inside specific subchips. manufacturing of test chips at Thesys Gesellschaft fur Mikroelektronik was accompanied by laser scattering after selected processed layers. Finally wafer maps based on electrically detected faults and optically detected particle defects were analyzed to determine correlations between defects and faults.

In-line defect inspection is of crucial importance in controlling the quality of VLSI manufacturing processes. Wafer inspection tools such as KLA 21XX coupled with the review/classification stations, such as KLA25XX can be extremely effective in detecting problems in the processed batches of wafers. However, there is a need to properly allocate these machines among several process steps (levels) to maximize their utilization. Moreover, results of this in- line inspection such as defect distributions, both spatial and size, could be used to predict the yield impact of the detected defects. Up to now, the so-called 'kill ratios' were used to indicate the yield impact of defects per layer (e.g., polysilicon, metal1, metal2). The typical accuracy of 'kill ratio' based prediction was around 25%. In this paper, we demonstrate the methodology of yield impact prediction based on critical area concept. Critical area is extracted from the actual product layout by a software tool called MAPEX developed at CMU. The information about defect densities and size distributions is obtained from KLA inspection equipment. A prototype of a software system was developed that combines the information about the critical area with the defect size distributions, declustering of defect data into a yield model. This methodology and software system were verified on the experimental data from AMD Austin fabrication facility. The 'yield impact' prediction (equivalent to 'kill ratio' prediction) was performed for 7 different products ranging from SRAM to microprocessor to telecommunication products. The data was collected from more than 2000 wafers. The accuracy of our prediction was verified by comparing our functional yield estimate to the actual yield values from the probe testing measurements. We obtained an accuracy of 1% for the defects found by KLA in h polysilicon layer for dies affected by single defects only. Moreover, we were able to normalize the defect inspection data for the entire product family. This was possible due to the availability of information about critical area for each of the product. Hence, we were able to demonstrate the advantage of this methodology of determining the 'kill ratios' for the defect inspection data.

This paper describes the integrated fast failure analysis/yield enhancement system used at Motorola's MOS-12 fab, established with the goal of providing high speed diagnostics and feedback. This goal was achieved through tight integration of in-fab inspection tools with electrical test equipment, out-of-fab analytical tools, and software tools. At this facility, the use of common file formats permits data exchange between wafer inspection tools, optical review stations, SEM, FIB, and electrical work bench testers. Wafer images generated at all diagnostic tools are stored on a video archival/retrieval system (VARS^TM). Correlation is a powerful tool for reducing failure analysis time and increasing failure analysis efficiency. By overlaying in-line inspection data with process, parametric, sort bin, and bitmap data, the locations of potential killer defects are rapidly identified. Physical failure analysis is performed on selected correlated failures to confirm the cause of device failures. Using analytical instruments with full wafer capability, in-line inspection or bitmap information are used to quickly locate the defects of interest. This approach has been successfully used to significantly reduce FA time compared with traditional FA methods. Fast failure analysis/yield enhancement is demonstrated with three case studies.

The discoloration of microchip bond pads due to the corrosive effects of the chemistries they are exposed to, poses a special problem for subsequent wire bonding operations. Such corrosion constitutes not only a cosmetic defect, but also interferes with the adhesion of the gold ball bonds to the bonding pads and compromises electrical connections to the device. These defects pose a serious reliability problem, and precautions must be taken in the manufacture of microelectronic devices to ensure that bond pad corrosion does not occur. This paper describes the phenomenon of bond pad staining/corrosion as well as the factors which influence its occurrence. A series of experiments were conducted to isolate and understand the corrosion mechanism, and the results of these experiments are presented. Finally, two different process modifications are presented which eliminate the occurrence of bond pad corrosion: a double sintering process, and the elimination of rf sputter etch prior to TiN ARC deposition on top layer metal.

In this work, time-dependent dielectric breakdown (TDDB) studies were performed on 6.5 nm, 9 nm, 15 nm, and 22 nm thick intrinsic SiO₂ films over a wide range of stress temperatures and electric fields both static and dynamic stress conditions. Results indicate that it is necessary to obtain data over a wide range of electric field to distinguish between the E and the 1/E models. Above 7 MV/cm both models fit well to the TDDB data. At lower electric fields, near operating conditions, oxide failure times vary exponentially with linear electric field and not with reciprocal field. The field acceleration parameter, gamma, is observed to be insensitive to temperature and has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied. The thermal activation energy, E_a, ranged between 0.7 to 0.95 eV for electric fields below 9 MV/cm. Contrary to the earlier studies, these results seem to provide consistent electric field and temperature dependencies for TDDB stress conditions indicating that the oxide films processed from different technologies have similar properties. Bipolar stress tests were performed at electric fields as low as 6 MV/cm and frequencies ranged from 1 kHz to 100 kHz. The results show that the increased lifetime observed under bipolar stress conditions diminishes as the stress electric field and oxide thickness are reduced. Capacitance-voltage measurements reveal different charge trapping characteristics at high and low electric fields of both static and dynamic stress. The results provide evidence that the mechanism of oxide breakdown at low electric fields is different from that at high electric fields and these two mechanisms appear to be a function of electric field and oxide thickness.

Results from this work suggest that multiple oxide traps with a distribution in time constants are generated during reactive ion etching (RIE) of gate antennas and that the amount of oxide degradation generated during plasma etching may be more substantial than that produced during plasma ashing. The oxide traps generated during RIE produce additional drain current fluctuations associated with the slow-state trapping and detrapping of channel electrons. It is found that the amplitude ((Delta) I_D) of these random telegraph signal (RTS) fluctuations may be modeled in terms of V_T increases and that (Delta) I_D scales as 1/L_eff². An example of circuit yield sensitivity to RIE over-etching effects in a Rockwell semiconductor systems production chip is presented. Prior to mask changes addressing an antenna effect, a large yield variance with a mean significantly lower than that predicted by the D_o of the process was observed. The large yield variance was attributable to a differential pair V_T mismatch induced by an antenna effect. After a simple lay-out change, a tight distribution near the predicted yield for the device was achieved. The analysis used to isolate the failure and the design fixes used to eliminate RIE effects are discussed.

The evolution of advanced packaging techniques like multi chip modules makes the realization of prototypes necessary. This can be a long and costly operation. Therefore we developed methods permitting time gains to be made in two of the steps of this operation. To avoid the use of physical masks we have experimented a laser beam set for direct writing of metal and insulating layers in microcircuits. To shorten preliminary tests, we propose a theoretical model of the interaction between the laser beam and the photoresist. It permits us to predict the line widths etched in the photoresist and thus avoids the need of long calibration processes. Electrical test lines of various widths have been used as a validation tool. The precision obtained is better than 5%. Polyimides (PI) meet most of the requirements for dielectric materials. As the curing process is crucial for the properties of the final PI film, thermal treatment was the subject of optimization leading however to process time up to more than 4 hours. We developed an interferometric control system in combination with a hot plate in order to provide an automated and optimized curing process. Total curing time is reduced to 1- 2 hours. Characterization and FTIR measurements were done for conventional and interferometrically controlled curing samples before and after aging in wet atmosphere: controlled samples are more crystalline, show comparable electrical and reliability properties, and seem less stressed.

The aim of this paper is a general survey of the test methods of analogue and mixed circuits, using a stimulus on the signal or power supply inputs, while the data came from the output current I_s or the power supply current I_DD. It insists on the fruitful measurement of I_DDQ, the dc power supply current, as well as the measurement of I_DDT, the transient power supply current. The design of a transducer has been performed. Its function is transparent because its power consumption is low and has no effect on the behavior of the circuit under test. This transducer is fast, accurate, linear and small for its possible duplication in the CUT. It can be inserted in mixed signal ASICs. Its performance in linearity and time domain allows us to exploit the advantages of the I_DD testing methods. This work is not a new approach of the fault detection but shows the application of new means for the static and dynamic measurements of I_DD.

The paper deals with testability analysis of differential ECL. The logic behavior and the drop in performance concerning a very detailed list of possible bipolar defects are examined. It is shown that at speed testing facilitates a rather high fault coverage of about 98% and that it is strictly necessary to test high speed integrated circuits at speed using BIST because automatic test equipment is only available up to clock frequencies of 660 MHz. The paper also deals with the design of high speed integrated circuits for test applications using differential ECL (emitter coupled logic). High operating speed can only be achieved if suitable circuit concepts (full custom designs) are chosen and the circuits themselves are carefully optimized. Circuits have been designed considering a low power consumption and a small overhead as they are used for testpattern generation (TPG) and signature analysis (SA) within a built-in self-test (BIST)-architecture. TPG and SA at datarates of several Gbit/s using LFSRs (linear feedback shift registers) are investigated.

The 5.2 M transistor UltraSPARC(TM)-I microprocessor is manufactured using the 0.5 micrometer EPIC3 CMOS QLM process. Design features were implemented to accelerate increases in manufacturing yield and product performance while enabling rapid establishment of high-coverage manufacturing test. Support for production memory defect mapping and repair, scan-based testing and failure analysis, component identity tracking, Iddq testing, per-chip CMOS process parameter monitoring, and aggressive process scalability were included. In implementing these features, our goal was to build a foundation for automatic and continuous identification of bottlenecks in performance of the overall microprocessor manufacturing process.

Yield is perhaps the single most important measure of manufacturing efficiency for large integrated circuits like UltraSPARC-I. To accelerate continuous yield improvement, we have integrated memory test, repair, and defect mapping into the UltraSPARC-I manufacturing flow. We use the UltraSPARC-I memory test port, together with standard memory test equipment and integrated software, to detect, locate and repair defects in the larger memory arrays. Pattern- recognized memory defect maps are collected for every chip manufactured, accelerating the understanding of defects and their causes. As part of the manufacturing process, we also program a unique identity into each chip that can be read electronically. In this paper, we present the memory defect mapping system that has been established and our use of that system to accelerate yield learning.

This paper reports a method for estimating critical areas and hence the yield of ULSI devices using survey sampling techniques. The approach does not suffer from the restrictions of previously reported methods of critical area estimation. In particular its practical application is not limited by the size of the device or the nature of the design hierarchy. The method makes possible, for the first time, efficient and accurate yield predictions of the most complex state-of-the-art devices using modest computing resources.

As the device sizes decrease and the number of interconnect levels and wafer size increase, the device yield and failure analysis becomes more complex. Currently, software tools are being used to perform visual inspection techniques after many operations during which defects are detected on a sample of wafers. However, it has been observed that the correlation between the yield predicted on the basis of the defects found during such observations and the yield determined electrically at wafer final test is low. Of a greater interest to yield/failure analysis software tools is statistical analysis software. SAS^TM can perform extensive data analysis on kerf test structures' electrical parameters. In addition, the software can merge parametric and yield/fail bins data which reduces the data collection and data reduction activities involved in the correlation of device parameters to circuit functional operation. The data is saved in large databases which allow storage and later retrieval of historical data in order to evaluate process shifts and changes and their effect on yield. The merge of process parameters and on-line measurements with final electrical data, is also possible with the aid of process parameter extraction software. All of this data analysis provides excellent feedback about integrated circuit wafer processing.

How can we optimize the data collection and data processing to provide us with the most significant information to drive the yield enhancement in a fast and efficient way? With the aim of facing this question this paper describes a software- system which is a part of the global yield enhancement strategy at our factory. The software developed correlates data gathered both in-line and at the end of the fabrication process. The description of the system is accompanied with descriptions of historical cases trying to show the capabilities of the type of correlation. The paper also discusses the natural expansion of the software-system to convert it into a more 'knowledge-based' tool.

As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to ensure that the shrinkage is done painstakingly to avoid unwanted leakage problems. This paper reports the discovery of two new failure mechanisms, short poly end-cap and silicon dislocation, that are found to cause subtle source drain leakage in sub-micron CMOS product. The electrical characteristics of the failure and the special techniques that are employed to fault isolate the problem are also discussed in this paper.

Due to increasing complex structures, such as multiple metal layers, high density circuits, and wide metal buses, on a die of an integrated circuit (IC) and specially packaged devices, such as flip chips and lead on chips, the traditional front side emission microscopy is no longer effective or cannot be applied. The back side emission microscopy is the alternative. It is a very useful, necessary, and complementary method to the front side emission microscopy in failure analysis. In this paper, photon emission mechanism and spectrum from a silicon die are first discussed. It explains that the emission intensity for the most occurred two emission types (forward and reverse biased junctions) from a die back side is about the same as or comparative to that from the die front side. Next, the five factors which mostly affect the emission intensity from the die back side are discussed. Last, several examples are given.

During the development of a 0.5 micrometer plug process (0.8 micrometer contacts), high temperature operating life tests for reliability indicated a failure mechanism caused by open contacts at contacts 2 and higher. Scanning electron microscope (SEM) images of cross-sections of opened contacts showed that the upper surface of the metal line was delaminating from the upper TEOS oxide and the tungsten plug. Further investigation revealed that delamination occurs even prior to W deposition, indicating that the real problem is with debonding at the top metal (TiW)-TEOS interface. Other symptoms of the problem are that it depends on contact geometry (contact size and enclosure) and is zonal. The extent of bad contacts also is sensitive to the type of etch used at contact resist strip; the situation improves when NOE is replaced by the milder ST22 strip. All of these symptoms can be understood in terms of stress- driven delamination at a poorly bonded interface. In this paper we present experimental results which show the effects of TEOS stress, film thickness, TEOS chamber 'season' (interfacial chemistry), metal surface treatments and contact resist strip on contact integrity. A model based on finite element calculations is presented that relates TEOS stress and contact geometry to the observed behavior. Following these findings, process changes were put in place to improve adhesion and to prevent notching (crack initiation) at the metal-oxide interface. Since adding these steps, the problem has not recurred.

Reactive ion etching (RIE) provides a rapid method for delayering integrated circuits. A problem that can prevent successful delayering is the 'grass' that sometimes occurs during plasma etching of silicon dioxide on integrated circuits by CF₄ or CF₄ plus O₂ plasmas. RIE grass is due to micro-etch-masking of the silicon dioxide surface by foreign materials. The consequence is poor delayering results. In this paper we demonstrate that RIE grass has three basic causes, each of which results in a different physical appearance. The first type of grass is due to sputter re-deposition of package materials such as gold. This can only be eliminated by masking the gold from exposure to the plasma. The second type of RIE grass is due to attack of exposed aluminum chip metallization which results in micro-etch-masking by aluminum or aluminum compounds. This can be avoided by eliminating O₂ from the gas supply whenever aluminum lines are exposed. The third type of grass is due to plasma etch chemistry which results in polymer formation on the sample surface. This can be eliminated by reducing the gas pressure which increases plasma potential and therefore increases sputtering.

Laser-assisted chemical vapor deposition (LCVD) of nickel from Ni(CO)₄ and copper from Cu(hfac)tmvs was utilized in the restructuring of an integrated circuit (IC) interconnection. Nickel and copper lines were deposited on passivated ICs by using a focused Ar⁺ laser beam to achieve new local rewirings on the chip. Nickel line depositions were carried out over the pressure range of 0.2 to 2.2 mbar of Ni(CO)₄ buffered in 200 - 800 mbar He. The typical laser beam scan speed was 24 micrometers per second for both metals. The Cu(hfac)tmvs precursor gas partial pressure was 0.3 mbar buffered in 10 mbar He or H₂ and typical laser scan speed was 24 micrometers per second. The morphology and chemical contents of the deposited interconnection microstructures was examined by atomic force microscopy (AFM), optical microscopy and laser ionization mass analysis (LIMA). The LIMA analysis indicated that the deposited copper surface was contaminated but the contamination level decreased when the layer was depth profiled. The deposited Ni lines were found to be pure Ni with only traces of carbon contamination. The utilization of XeCl excimer laser in the cutting of Al and Mo conductor lines and passivation contact via opening for IC modification is also described. LCVD method was successful in numerous different IC failure inspection and circuit modification cases.

Pipeline defects have recently been reported in a leakage source of CMOS devices when die shrink. We report the observed physical defects which shorted source and drain under .6 u short channel CMOS devices by the Wright-etching of the defective devices. We also found pipeline defects filled with phosphorous doped n-type material by the cross- sectioning of the pipeline in the channel of NMOS transistor. We also observed that devices are failing during high temperature reliability test, which causes single bit failure. This indicates that there are many potential defective die to reach assembly process even though most of detectives are discarded at wafer sort. SEM analysis identifies that location of defective parts is decorated with a pair of protruding holes at the 90 degree corner of field island of faulty pass-gate of SRAM. These pipeline defects are caused mainly by the compressed stress from field oxide. Reliability and yield have been improved since the pipeline were minimized after relieving stress on pass- gate.

With the ever increasing complexity in IC design and with the introduction of flip chip technology, the pressing need for computer aided fault isolation (FI) is sensed. Fanin tree is a collection of subsequent fan-in signals with respect to a given node. As such, possible failing locations can be narrowed down to nodes that reside within the fanin tree only. Multiple fanin trees from multiple known failing nodes can also be intersected to locate common driving nodes. This paper presents an application program that was developed for Intel standard (.sch) netlist format. The result is FTREE; a fanin tree tool that is independent of product. This tool enhances the performance of other FA tools; but for its optimum usage, proper scan node selection is required during design stage. Selection of these nodes also is presented.

We have developed a set of analysis tools to accelerate root-cause understanding of any UltraSPARC^TM-I microprocessor manufacturing process or design problems encountered on the path to volume manufacturing ramp. We also use these tools to understand root-cause of yield or performance limitations. The custom hardware and software developed to support UltraSPARC^TM-I debug is presented, followed by a discussion of our debug methodology. We conclude with an example use of the tools and methods presented to analyze and resolve an actual problem experienced during UltraSPARC^TM-I manufacturing start- up.

The UltraSPARC-I microprocessor is tested at several stages in the manufacturing flow to screen out any chips which contain manufacturing defects and to sort chips by speed. Custom test hardware and software have been developed to perform production test of UltraSPARC-I in both wafer and packaged form. To speed up chip yield and performance improvement, we collect detailed yield and performance measurement data during test of every microprocessor manufactured. The data collected includes detailed pass or fail results of individual patterns, performance measurements of maximum operating frequency and Vcc, parametric measurements of transistor saturation currents and ring oscillator frequencies, and Idd measurements. The goal of our data collection is to provide, without the need for engineering retest, immediate diagnostic information on why each chip yielded and performed as it did, enabling yield and performance issues to be quickly identified and subsequently resolved.

Rapidly changing demands in the microprocessor industry require that new products be quickly brought to volume production on the fastest fabrication process available. Two key metrics of success for manufacturing start-up of a microprocessor are manufacturing yield and product performance. We have developed a comprehensive data collection and analysis system to speed identification, measurement, diagnosis and resolution of yield and performance bottlenecks and therefore accelerate yield and performance improvement of the UltraSPARC-I microprocessor. Our system is based on automated collection of wafer processing and electrical parametric data plus detailed defect map, test and performance data collected for every microprocessor manufactured. This system and its application to yield and performance improvement are presented in this paper.

For process control and yield improvement, in-line inspection and defect review are required in the semiconductor industry. In order to monitor the process and be able to identify and solve any production related problems, the review must use a precise defect classification. For effective classification, the defects must first of all be analyzed and identified and the defect classes created. Defect characterization can be performed using different kinds of tools: optical microscope, electron microscope with x-ray analysis and others. In-line review and classification are mainly achieved using optical systems because of their throughput. However this technique is not efficient enough for advanced technologies. Scanning electron microscopy with EDX analysis must be used in order to accurately determine the defect classes. The SEM resolution, type of image contrast and the possibility of performing chemical analyses using the EDX system can lead to a change in the classification, set up by optical review. Defect characterizations are presented and on some examples the limitations of optical classification and the interest of SEM and EDX analyses in determining the defect classes are highlighted.

Plasma contamination in a 0.35 micrometer triple-level metal CMOS process was investigated in response to anomalous dc parametric test data. Electrical PMOS transistor performance and both physical and electrical gate oxide thickness were significantly degraded upon exposure of a sacrificial oxide to a plasma ash following a masked, P-channel threshold adjust ion implant. The contamination was isolated to a specific asher, found to be radial in nature across a wafer, and consistently worse in one of the two chambers used during the ash process. The contamination dramatically reduced the wet etch rate of the sacrificial oxide, leading to incomplete removal prior to gate oxide growth. Increasing the wet strip time of the sacrificial oxide improved the ability to remove this contaminated film, but was limited by minimal field oxide thickness requirements to avoid field inversion. Transferring the ash process to an alternative, low-damage, down-stream asher eliminated the plasma contamination.

Over the last 12 months, Austria Mikro Systeme has installed an even more rigorous system of defect density measurement, monitoring and control in its facility at Unterpremstatten. To accomplish this, 2 test devices (Medusa 1 and 2) were designed which allow possible defects in all layers of the process to be located. These devices are 8 by 9 mm² in area and contain various structures to quantify the density of defects causing continuity, bridging and inter-layer isolation failure. The devices move through the waferfab receiving all process steps with the usual handling and operator procedures, from which it is clear, that the density of defects measured is representative of that of normal production material. The wafers are tested electrically using a Keithley S450, and data analysis is done with RS1 and EXCEL. By using yield models available from the literature, the correspondence in yield estimates made in this way and actual production yields were generally within 3%. Applying this technique allows the yield loss mechanisms to be isolated and then prioritized. The chipset identified several areas within the process which required special attention. These included implant optimization to reduce gate oxide damage, defect reduction in the metal-etch process, increased leakage currents caused by implant channeling and second poly etch-control to avoid 'bridging' around poly 1 periphery. Successful actions at these points have led to a significant improvement in wafer probe yields at Austria Mikro Systeme.

We have constructed an automated laser scanning complex oriented to semiconductor wafers defectiveness monitoring. The surface photo-voltage method has proved to be sensitive to various types of surface contamination and damages. The fractal approach used for the first time for theoretically maximal value of VLSI yield estimation has demonstrated high prognostic ability.

This paper presents the modern concept of the new application of focused ion beam techniques to some failure analysis such as microscopic selective cross sectioning and in-situ observation of the cross section, respective to the observation of the aluminum microstructure. The system configuration is presented with main functions first of all. The procedure shows for microscopic cross sectioning and in- situ observation uses etching function and the SIM function too. This permits us to do new approaches for failure analysis and process monitoring such as microscopic cross- sectioning and in-situ observation which have been achieved by means of the combination of the microscope etching and the SIM (scanning ion microscope) functions. The examples of analysis for electromigration failure and two process anomalies have been shown. The new method is not only less time consuming but easier to use than the conventional methods and also has new functions such as multiple microscopic cross-sectioning and continuous micro-slicing. The observation of aluminum microstructure has been achieved by means of the SIM function. The comparison of SIM and TEM images has been achieved and it has been shown that the sum of SIM images at different titled angles is useful to analyze grain size distributions. In practice even a single image of SIM is enough to analyze grain size distributions. The comparison of SIM and SEM images has shown that the SEM image does not show the real microstructure of aluminum. Therefore we should not use SEM as a tool for microstructure analysis. The new method is less time consuming and easier to use than the conventional TEM method. As an extension of this new concept of analysis by FEB the combination of both approach modes it is possible to observe the microstructure at the cross section of aluminum. This concept, successfully recommended for silicon technologists in VLSI manufacturing, makes some failure analysis simpler and less time consuming.

Industrial Engineering is fairly new to the semiconductor industry, though the awareness to its importance has increased in recent years. The US semiconductor industry in particular has come to the realization that in order to remain competitive in the global market it must take the lead not only in product development but also in manufacturing. Industrial engineering techniques offer one ofthe most effective strategies for achieving manufacturing excellence. Industrial engineers play an important role in the success of the manufacturing facility. This paper defines the Industrial engineers role in the IC facility, set the visions of excellence in semiconductor manufacturing and highlights 10 roadblocks on the journey towards manufacturing excellence. Keywords: industrial engineering, semiconductor, manufacturing, productivity improvement, modeling, design

Wire length reduction along with via minimization results in better performance and higher yield for VLSI circuits. In this paper we present a wire length reduction algorithm for channel routing. The results of our algorithm for a set of benchmark examples are presented. The algorithm produces near optimal results for most of the examples. Surprisingly, our algorithm outperforms most of the previously proposed via minimization algorithms as well. Our results show that both wire length and via minimization problems are closely related to each other but their optimal solutions don't necessarily coincide.

Submicron CMOS VLSI wafer product yield problems were correlated with a high p⁺ contact resistance in an Al/TiN/Ti/TiSi₂/Si structure. Electrical measurements of contact resistance kelvin (non-interface) versus (interface) contact test structures were used to isolate the high resistance path. Secondary ion mass spectrometry (SIMS) analysis showed good correlation between the Ti to TiSi₂ formation and different anneal conditions. The analysis also showed a strong relationship between TiSi₂ formation and p⁺ surface concentration and junction depth. Deeper boron penetration into the silicon will occur with incomplete silicide penetration. The analytical data showed the changes in processing necessary to eliminate the resistance problem and achieve high dopant surface concentration and the desired junction depth.