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12 September 1996 Built-in self-test for high-speed integrated circuits
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The paper deals with testability analysis of differential ECL. The logic behavior and the drop in performance concerning a very detailed list of possible bipolar defects are examined. It is shown that at speed testing facilitates a rather high fault coverage of about 98% and that it is strictly necessary to test high speed integrated circuits at speed using BIST because automatic test equipment is only available up to clock frequencies of 660 MHz. The paper also deals with the design of high speed integrated circuits for test applications using differential ECL (emitter coupled logic). High operating speed can only be achieved if suitable circuit concepts (full custom designs) are chosen and the circuits themselves are carefully optimized. Circuits have been designed considering a low power consumption and a small overhead as they are used for testpattern generation (TPG) and signature analysis (SA) within a built-in self-test (BIST)-architecture. TPG and SA at datarates of several Gbit/s using LFSRs (linear feedback shift registers) are investigated.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Udo Jorczyk and Wilfried Daehn "Built-in self-test for high-speed integrated circuits", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996);

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