12 September 1996 Design of the UltraSPARC-I microprocessor for manufacturing performance
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The 5.2 M transistor UltraSPARC(TM)-I microprocessor is manufactured using the 0.5 micrometer EPIC3 CMOS QLM process. Design features were implemented to accelerate increases in manufacturing yield and product performance while enabling rapid establishment of high-coverage manufacturing test. Support for production memory defect mapping and repair, scan-based testing and failure analysis, component identity tracking, Iddq testing, per-chip CMOS process parameter monitoring, and aggressive process scalability were included. In implementing these features, our goal was to build a foundation for automatic and continuous identification of bottlenecks in performance of the overall microprocessor manufacturing process.
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Lynn Youngs, Lynn Youngs, Greg Billus, Greg Billus, Anjali Jones, Anjali Jones, Siva Paramanandam, Siva Paramanandam, } "Design of the UltraSPARC-I microprocessor for manufacturing performance", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250825; https://doi.org/10.1117/12.250825

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