12 September 1996 Inter- and intra-die polysilicon critical dimension variation
Author Affiliations +
Abstract
A methodology has been developed as part of a statistical metrology framework (1) to assess the relative range and distribution of intra-die, or die-level, polysilicon critical dimension variation as opposed to wafer-level, or inter-die, poly-CD variation; (2) to identify the key layout factors involved in poly-CD intra-die variation; and (3) to develop first-order semi-empirical models for poly-CD variation. A new approach utilizing multivariate analysis of variance methods is described to model the die- and wafer- level variation components. We show that pattern dependent variation is approximately twice as large as wafer-level variation. In addition, we find that spatial position plays a strong role: the first-order pattern dependent variation model (or die 'signature') shows a strong dependence on spatial position across the wafer, and individual components of the model demonstrate different spatial position sensitivities.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Brian Stine, Brian Stine, Duane S. Boning, Duane S. Boning, James E. Chung, James E. Chung, David A. Bell, David A. Bell, Edward Equi, Edward Equi, } "Inter- and intra-die polysilicon critical dimension variation", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250826; https://doi.org/10.1117/12.250826
PROCEEDINGS
9 PAGES


SHARE
Back to Top