12 September 1996 Wire length and via reduction for yield enhancement
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Wire length reduction along with via minimization results in better performance and higher yield for VLSI circuits. In this paper we present a wire length reduction algorithm for channel routing. The results of our algorithm for a set of benchmark examples are presented. The algorithm produces near optimal results for most of the examples. Surprisingly, our algorithm outperforms most of the previously proposed via minimization algorithms as well. Our results show that both wire length and via minimization problems are closely related to each other but their optimal solutions don't necessarily coincide.
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Venkat K. R. Chiluvuri, Venkat K. R. Chiluvuri, Israel Koren, Israel Koren, } "Wire length and via reduction for yield enhancement", Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250850; https://doi.org/10.1117/12.250850

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