13 September 1996 Gate oxide field design in the sub-10-nm region
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Abstract
This paper discusses the gate oxide fields for MOS LSI design in the sub-10 nm gate oxide region for the nearest next few generations. Since practical determination of allowable gate oxide fields for scaled gate oxides strongly depends on oxide defect density levels, we measured defect densities for gate oxide thicknesses down to 3 nm. The defect-related breakdown failures affecting reliability were found to decrease with decreasing gate oxide thickness. The allowable gate oxide fields were calculated as a function of the gate oxide thickness and gate area to meet reliability criteria. The discussion also includes recent key issues such as the contribution of high-quality wafer substrates to allowable electric fields, and design guidelines for dual power supply voltages. Since the defect density levels depend on process, we generalized our discussion by showing the results for various gate areas.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Katsuhiko Kubota, C. Suzuki, Kosuke Okuyama, N. Suzuki, "Gate oxide field design in the sub-10-nm region", Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250869; https://doi.org/10.1117/12.250869
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