Interconnection schemes for parasitics optimization

Nicolas Delorme; Marc Belleville; Sylvette Bisotto; Jean Chilo

doi:10.1117/12.250885

13 September 1996 Interconnection schemes for parasitics optimization

Nicolas Delorme, Marc Belleville, Sylvette Bisotto, Jean Chilo

Proceedings Volume 2875, Microelectronic Device and Multilevel Interconnection Technology II; (1996) https://doi.org/10.1117/12.250885
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

A set of four interconnection schemes is proposed to reduce parasitic ground and coupling capacitances and thus enhance technology performance. These strategies consist in: increasing the inter-metal dielectric thicknesses, using SiOF instead of SiO₂, embedding the interconnects in a low-permittivity dielectric and switching to copper metallizations with constant line resistance. The effectiveness of these schemes is checked for the capacitances of simple 2D structures, for delay, crosstalk, and consumption in standard circuit routings, and for a 32 bits adder worst case delay and consumption.

Citation Download Citation

Nicolas Delorme, Marc Belleville, Sylvette Bisotto, and Jean Chilo "Interconnection schemes for parasitics optimization", Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); https://doi.org/10.1117/12.250885

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