Lg=0.25-um CMOS devices with N+-polycide gate for 3.3-V application

Jeong Yeol Choi; Zhijian Ma

doi:10.1117/12.250861

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13 September 1996 Lg=0.25-um CMOS devices with N⁺-polycide gate for 3.3-V application

Jeong Yeol Choi, Zhijian Ma

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Proceedings Volume 2875, Microelectronic Device and Multilevel Interconnection Technology II; (1996) https://doi.org/10.1117/12.250861
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

A single N+ polycide gate CMOS process in 0.25 micrometers gate-length regime for 3.3 V application is presented with emphasis on process control, reliability and manufacturability. Key process steps include super-steep retrograde twin N/P wells, 70 angstroms gate oxide, shallow LDD implants, 1000 angstroms spacer, and 800 degree(s)C/60 minute furnace annealing. Process parameters such as implant energy and oxide thickness were chosen for good control and manufacturability. Devices show excellent I-V characteristics, subthreshold slopes and good suppression of short-channel effects such as punch-through, VT roll-off, DIBL and high-field effects for 3.3 V applications. The devices are optimized with a trade-off between performance and reliability by adjusting physical dimension and doping concentration in the LDD region. A gate delay of 27 ps/stage at 3.3 V has been realized for 0.25 micrometers N+-polycide gate CMOS technology.

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Jeong Yeol Choi and Zhijian Ma "Lg=0.25-um CMOS devices with N⁺-polycide gate for 3.3-V application", Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); https://doi.org/10.1117/12.250861

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