Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C

Dirk Uffmann; Christina Ibrom; Joerg Ackermann; Jens Stemmer; Jochen Aderhold

doi:10.1117/12.250891

13 September 1996 Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C

Dirk Uffmann, Christina Ibrom, Joerg Ackermann, Jens Stemmer, Jochen Aderhold

Proceedings Volume 2875, Microelectronic Device and Multilevel Interconnection Technology II; (1996) https://doi.org/10.1117/12.250891
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

Due to economical reasons junction isolated CMOS should be extensively exploited for temperature resistant electronics. A limitation at high temperatures is given by parasitic effects in the substrate, namely leakage currents, latch-up, and snap-back. Snap-back is caused by the parasitic bipolar action of single MOS transistor structures. We have investigated the temperature dependence of the snap-back phenomenon up to 250 degree(s)C using silicided LDD-MOS transistors with gate lengths of 0.8 micrometers and 1.0 micrometers as test devices. Measurements were performed dynamically with short pulses of rectangular shape. The snap-back breakdown voltage of 0.8 micrometers NMOS transistors decreases from 14.3 V at room temperature to 10.6 V at 250 degree(s)C and the triggering voltage for second breakdown from approximately 9.4 V at RT to 6.2 V at 250 degree(s)C. For PMOS transistors no snap-back was observed up to 20 V pulse height. The results show that snap-back is not a problem for this CMOS process up to the specified power supply voltage of 5 V. To consider shrinking effects were performed 2-dim FEM simulations. At high temperatures, the breakdown voltage is reduced with increasing temperature and decreasing gate length. This correlates to a value of the current gain of the parasitic bipolar transistor (beta) > 1 at the breakdown point. The commonly applied measures for designing processes with shorter gate lengths, like e.g. higher tub doping, are also sufficient to avoid snap-back under bias conditions even at temperatures up to 250 degree(s)C.

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Dirk Uffmann, Christina Ibrom, Joerg Ackermann, Jens Stemmer, and Jochen Aderhold "Snap-back temperature dependence for an Epi-CMOS ASIC-process up to 250 degrees C", Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); https://doi.org/10.1117/12.250891

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KEYWORDS

Transistors

Vestigial sideband modulation

Doping

Temperature metrology

Electronics

Measurement devices

Molybdenum

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