13 September 1996 Study of integration issues in shallow trench isolation for deep submicron CMOS technologies
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Abstract
This paper presents a study of the issues in integrating the pattern, fill, planarization and surface cleanup processes to design a shallow trench isolation (STI) flow suitable for 0.25 micrometers CMOS technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data is presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.
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Amitava Chatterjee, Amitava Chatterjee, Mark E. Mason, Mark E. Mason, K. Joyner, K. Joyner, Daty Rogers, Daty Rogers, Doug Mercer, Doug Mercer, John Kuehne, John Kuehne, A. L. Esquivel, A. L. Esquivel, P. Mei, P. Mei, Suhail S. Murtaza, Suhail S. Murtaza, Kelly J. Taylor, Kelly J. Taylor, Iqbal Ali, Iqbal Ali, S. Nag, S. Nag, Sean C. O'Brien, Sean C. O'Brien, S. Ashburn, S. Ashburn, Ih-Chin Chen, Ih-Chin Chen, } "Study of integration issues in shallow trench isolation for deep submicron CMOS technologies", Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250874; https://doi.org/10.1117/12.250874
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