Use of elevated source/drain structure in sub-0.1 um NMOSFETs

Jay J. Sun; Jiunn-Yann Tsai; Kam F. Yee; Carlton M. Osburn

doi:10.1117/12.250863

13 September 1996 Use of elevated source/drain structure in sub-0.1 um NMOSFETs

Jay J. Sun, Jiunn-Yann Tsai, Kam F. Yee, Carlton M. Osburn

Proceedings Volume 2875, Microelectronic Device and Multilevel Interconnection Technology II; (1996) https://doi.org/10.1117/12.250863
Event: Microelectronic Manufacturing 1996, 1996, Austin, TX, United States

Abstract

As MOSFET feature sizes are scaled down to 0.1 micrometers and below, new techniques are required to develop and fabricate shallow, low contact resistance, and low leakage S/D junctions. In this study, 2D device simulations have been performed to compare conventional drain/source extension and elevated source/drain structure approaches for sub-0.1 micrometers MOSFETs. With a relatively deep n+ junction (approximately 0.1 micrometers ) in the D/S extension structure, the sidewall spacer needs to be wide enough such that the n+ front is away from the gate edge in order not to contribute significantly to short-channel effects due to additional charge sharing and drain-induced-barrier-lowering (DIBL). However this requires increased device layout area and results in increased parasitic resistance due to the long and shallow D/S extensions. Elevated S/D structures offer an alternative solution by providing a sacrificial layer for silicidation and a shallow n+ junction in the substrate to minimize the impact of n+ junctions on short-channel effects in sub-0.1 micrometers devices. The use of elevated S/D structure allows scaling down of the spacer width and relaxing the subsurface doping requirement to achieve a specified DIBL level. These lead to a significant increase in the drive current and a reduction in the junction capacitance. The gate-to-S/D capacitance associated with elevated S/D MOSFET can be controlled by proper scaling of the elevated layer thickness along with other pertinent design parameters.

Citation Download Citation

Jay J. Sun, Jiunn-Yann Tsai, Kam F. Yee, and Carlton M. Osburn "Use of elevated source/drain structure in sub-0.1 um NMOSFETs", Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); https://doi.org/10.1117/12.250863

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