One of the main challenges for the industrialization of the alternating phase shift mask technique is the geometrical design of the phase shifters. The problem is complex and software development is required to achieve automation. This data preparation is necessary in order to apply the most powerful optical enhancement technique, the alternating PSM, to the gate lithography of logic designs. After the implementation of an algorithm, very promising on small flat geometrical designs of a few hundred transistors, it has been decided to test this software on complete circuits. This paper deals with the issues associated with alternating pattern generation on complex circuits. In particular, the use of layout hierarchy is essential to obtain an acceptable amount of manual intervention and computer processing time. There are two kinds of limitations to this global approach. First, the overlapping or the proximity of cells in the hierarchy may not be compatible with a cell-by-cell generation of phase shifters. Secondly, some local design configurations may be difficult to phase shift. The question is: `is the number of occurrences of such cases manageable?' This presentation is illustrated by our experience on a multiplier design of about 15000 transistors, created using a standard cell library in 0.25 micron technology. This work shows that the theoretically difficult cases of layout hierarchy or geometrical design are not critical in practice. In particular, the design method based on standard cell libraries creates a hierarchy which is very favorable to our approach. This article presents a method for the alternating pattern generation on complex circuits which is based on two main points: first, on a software able to generate alternating phase shifters on small flat cells, and secondly, on the advantage of using layout hierarchy.