Hierarchical decomposition model for reconfigurable architecture

Simsek Erdogan; Abdul Wahab

doi:10.1117/12.255811

21 October 1996 Hierarchical decomposition model for reconfigurable architecture

Simsek Erdogan, Abdul Wahab

Proceedings Volume 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic; (1996) https://doi.org/10.1117/12.255811
Event: Photonics East '96, 1996, Boston, MA, United States

Abstract

This paper introduces a systematic approach for abstract modeling of VLSI digital systems using a hierarchical decomposition process and HDL. In particular, the modeling of the back propagation neural network on a massively parallel reconfigurable hardware is used to illustrate the design process rather than toy examples. Based on the design specification of the algorithm, a functional model is developed through successive refinement and decomposition for execution on the reconfiguration machine. First, a top- level block diagram of the system is derived. Then, a schematic sheet of the corresponding structural model is developed to show the interconnections of the main functional building blocks. Next, the functional blocks are decomposed iteratively as required. Finally, the blocks are modeled using HDL and verified against the block specifications.

Citation Download Citation

Simsek Erdogan and Abdul Wahab "Hierarchical decomposition model for reconfigurable architecture", Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); https://doi.org/10.1117/12.255811

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