For a number of years, we have studied the large-scale fine-grained limit of cellular-logic-array calculations and
computers-with particular emphasis on applications to physical simulation. Perhaps the most relevant lessons
of this work for the FPGA community have to do with the applicability of virtual-processor techniques to these
logic-array computations-and by extension to the design of FPGA's themselves. These techniques allow us to
tradeoff speed against size, to balance resources devoted to data storage with those devoted to processing, and
to time-share communication resources as we share processors. An application area of particular interest to the
FPGA community is in logic emulation, where a virtual processing approach lets us maximize useful processor
cycles by having processing hardware follow computational wavefronts through arrays of virtual logic ("temporal
pipelining"). This technique is of direct relevance to FPGA design.
Our virtual processor approach is embodied in our indefinitely scalable cAM-8 cellular automata (CA) machine.
Personal-computer-scale prototypes, designed and built at MIT using 1988 technology, are still about as fast as
any conventional computer for most large-scale physical CA applications. Using today's high-bandwidth DRAM'S,
machine's with the same number of memory chips could be built that run 100 times faster. Rather than build a
new dedicated CA machine processor, it is attractive to instead add appropriate DRAM I/O and data-buffering
circuitry to an FPGA design, to create a general-purpose class of FPGA's optimized for large-scale virtualprocessor