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21 October 1996 Polynomial-transform-based approach to computing 2D DFTs using reconfigurable computers
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Abstract
Considerable success has been achieved in developing signal processing algorithms that are efficient from the standpoint of number of operations. However, what is needed now is to develop new algorithms which are better adapted to existing hardware, or to device new architectures that more efficiently exploit existing signal processing algorithms. This latter approach forms the basis of this paper. An FPGA architecture is described that takes advantage of the reduced computational requirements of the polynomial transform method for computing 2-D DFTs. The performance of the architecture is presented and is shown to use 36% less FPGA resources than a row-column DFT processor. A multi-FPGA architecture is described that is capable of processing 24 512 by 512 pixel images per second. The multi-FPGA processor is 46% more area efficient than a row-column DFT implementation.
© (1996) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chris H. Dick and Fred J. Harris "Polynomial-transform-based approach to computing 2D DFTs using reconfigurable computers", Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); https://doi.org/10.1117/12.255837
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