VBR traffics with their bursty nature are still troublesome for ATM networks. The problem can be dealt with in call admission and bandwidth allocation stages and later, when the connection is established, by appropriate flow control schemes and buffer allocation mechanisms. Accommodating the large bursts in extra buffers at the inputs of switch fabric, during the overflow periods in the internal buffers, can be part of the solution given to this problem. Adding the input buffers is more preferable than expanding the internal memory because the input buffers are less expensive and can be used in bulk, while the internal buffers are more complex and expensive and not easily expandable. In this paper we consider a general model for switches with input buffers which consists of three parts: input buffer, I/O flow controller, and output (internal) buffer. In this way we isolate the switching mechanism and the back-pressure mechanism required in this kind of switches. We present different architectures for the I/O flow controller section and discuss the advantage and disadvantages of each model. We also address the QoS requirements of the individual connections in the input buffered switches by providing a specific architecture for the input buffer which unlike the traditional FIFO buffers allows scheduling the service among the cells in the input buffer without extra complexity.