Paper
4 April 1997 Experimental performance of an ATM-based buffered hyperplane CMOS-SEED smart pixel array
Stefan K. Griebel, M. Richardson, K. E. Devenport, Harvard Scott Hinton
Author Affiliations +
Abstract
An ATM-based buffered HyperPlane smart pixel array (SPA) utilizing the Hybrid CMOS-SEED technology has been designed, fabricated, and tested. Multiple quantum well p-i-n photodiodes (SEEDs) are used as the optoelectronic interface in the SPA. The SPA consists of a 4 X 9 array of smart pixels comprised of 4 parallel ATM node channels. The chip fabricated is an experimental version extensible to a 256 X 256 array for implementing an ATM-based HyperPlane switching architecture on a free space optical backplane. Experimental performance of the SPA is presented.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Stefan K. Griebel, M. Richardson, K. E. Devenport, and Harvard Scott Hinton "Experimental performance of an ATM-based buffered hyperplane CMOS-SEED smart pixel array", Proc. SPIE 3005, Optoelectronic Interconnects and Packaging IV, (4 April 1997); https://doi.org/10.1117/12.271093
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Cited by 4 scholarly publications.
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KEYWORDS
Asynchronous transfer mode

Logic

Optical fabrication

Clocks

Free space optics

Free space

Interfaces

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