4 April 1997 Processor arrays with asynchronous TDM optical buses
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Abstract
We propose a pipelined asynchronous time division multiplexing optical bus. Such a bus can use one of the two hardwared priority schemes, the linear priority scheme and the round-robin priority scheme. Our simulation results show that the performances of our proposed buses are significantly better than the performances of known pipelined synchronous time division multiplexing optical buses. We also propose a class of processor arrays connected by pipelined asynchronous time division multiplexing optical buses. We claim that our proposed processor array not only have better performance, but also have better scalabilities than the existing processor arrays connected by pipelined synchronous time division multiplexing optical buses.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Y. Li, Y. Li, S. Q. Zheng, S. Q. Zheng, } "Processor arrays with asynchronous TDM optical buses", Proc. SPIE 3005, Optoelectronic Interconnects and Packaging IV, (4 April 1997); doi: 10.1117/12.271100; https://doi.org/10.1117/12.271100
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