17 January 1997 New architecture for MPEG-2 real-time encoding
Author Affiliations +
Abstract
A new architecture for real-time MPEG-2 encoding/decoding is presented in this paper. This architecture is based on an array of TI MVPs. The main feature of this architecture is its programmability. The inherent parallelism of the MPEG-2 algorithm is investigated in order to map it to the processor array. An I/O algorithm for the major encoding function, motion estimation, is developed to demonstrate the possibility of overlapping processing and I/O.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mansour Zuair, Dikran S. Meliksetian, C. Y. Roger Chen, "New architecture for MPEG-2 real-time encoding", Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); doi: 10.1117/12.263510; https://doi.org/10.1117/12.263510
PROCEEDINGS
12 PAGES


SHARE
RELATED CONTENT

Scalable video coding based on Wyner-Ziv framework
Proceedings of SPIE (July 31 2006)
DSP-based real-time video encoding
Proceedings of SPIE (April 19 2000)
DM642 digital media processor
Proceedings of SPIE (May 07 2003)
Single board H.261 video codec
Proceedings of SPIE (February 17 1995)
Compressed-domain reverse play of MPEG video streams
Proceedings of SPIE (January 22 1999)

Back to Top