Lately, VLIW architectures have become popular because of their good cost-performance ratio for e.g. multimedia applications. Multimedia applications are characterized by regular signal processing and, therefore, they are apt for analysis by compilers. VLIW architectures exploit this by scheduling the instruction stream at compile time and, thus, reducing the complexity and costs of instruction issue hardware. However, sometimes we encounter signal processing algorithms that we would like to be regular and predictable but that are so only to a certain extent. Polyphase filtering is one such algorithm. It contains a regular filter part, but its input and output streams run at rates that are not correlated to each other in a simple way. Compile time analysis is, therefore, only partly possible, which poses an inherent problem for VLIW architectures. In this paper, we describe the steps that we went through to optimize the polyphase filter for a specific instance of a VLIW architecture: the Philips TriMedia processor. We show which architectural features help to make the TriMedia processor more efficient for such irregular algorithms.