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19 June 1997 Clock multiplier with a range up to 370 MHz for video/display signal processing
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This paper describes the design of a clock generation circuitry to be used as part of an affordable gigabit module head mounted display. A self-calibrated tapped delay line is used to generate different clock signals, which are then passed through logical function to produce an integral- multiple of an input clock. The system is fabricated on 0.8 micrometers CMOS triple layer using MOSIS CMOS process. All processes technology can operate at 3.3 V or 5.0 V. Experimental results show a realization of 4 times clock multiplier circuit with an output range of up to 370 MHz with almost zero-clock skew. The proposed clock multiplier circuitry is simple, temperature independent, uses a very small number of transistors and hence requires less area and power dissipation than earlier realizations.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Rida Hamza "Clock multiplier with a range up to 370 MHz for video/display signal processing", Proc. SPIE 3046, Smart Structures and Materials 1997: Smart Electronics and MEMS, (19 June 1997);


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