Measuring and inspecting the topography of very small features during the fabrication of VLSI devices plays a major role in process control and production yield enhancement. Optical and confocal microscopes lack the resolution needed for today's most advanced processes. Atomic Force Microscopy provides the necessary x, y, and z measurements, but is relatively slow and has limitations due to the necessity of placing a probe with finite size into circuit structures. Scanning electron microscopy (SEM) is today's preferred technology for this task. However, traditional SEM images have a 'flat' vertical appearance, and do not present an accurate representation of the actual surface topography. Tilted SEMs provided a view of wafer topography, but they are slower and are limited to projectile images of the device which do not always show complete structures such as contact holes. A multiple detector SEM enables the development of a method for producing high resolution images of the sample's surface. These images, processed on silicon graphics work stations, produce 3D renditions of the surface from different points of view while maintaining the capability of visualizing complete surface features. In this paper we describe the above method, and provide results, including sample surface profiles and images obtained from actual wafer samples.