As semiconductor technology continues its way towards smaller geometries, CMP has gained acceptance as the planarization technique for interconnect layers. Its benefits are well known, especially in terms of imaging. However, one of its major drawbacks is to make difficult the alignment of interconnect layers, since a planarized alignment mark is less visible for the stepper's alignment system. Usual workarounds include the clearing of process layers from the alignment mark before exposing the product layer. Although these workarounds provide a temporary solution, they are too costly to be viable in a mass production environment. In this experiment, a non-zero alignment strategy using new mark designs has been tested on the backend layers of a 0.35 micrometers CMOS process. New mark designs have been evaluated, where the space part of the gratings has been filled with 'segments' of various width, the purpose being to minimize the planarization effect of the metallization process. For the selection of the best mark design, several criteria have been taken into account: the stepper's built-in alignment diagnostic software provides information on the quality of the alignment signal. The most important criterion is the product overlay measurement and its repeatability. Marks cross sections using a FIB/SEM tool give indications on the mark profile after metal deposition.