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7 July 1997 NA/σ optimization strategies for an advanced DUV stepper applied to 0.25-μm and sub-0.25-μm critical levels
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Abstract
In this paper, the results of an NA-sigma optimization study are reported, carried out experimentally for an advanced ASML PAS5500/300 deep-UV stepper. The work has been primarily focused on a 0.25 and sub-0.25 micrometers gate layer in a logic CMOS process. A positive and negative tone resist process have been compared in terms of CD control and line- end shortening. Dry etch effects and across-field behavior has been taken into account. Furthermore the contact level of the 0.25 micrometers process have been optimized. Effects of layer dependent NA-sigma settings on overlay have been studied.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Maaike Op de Beeck, Kurt G. Ronse, Kouros Ghandehari, Patrick Jaenen, Harry Botermans, Jo Finders, John A. Lilygren, Daniel Claire Baker, Geert Vandenberghe, Peter De Bisschop, Mireille Maenhoudt, and Luc Van den Hove "NA/σ optimization strategies for an advanced DUV stepper applied to 0.25-μm and sub-0.25-μm critical levels", Proc. SPIE 3051, Optical Microlithography X, (7 July 1997); https://doi.org/10.1117/12.275973
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