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15 July 1997 Integrated three-tiered approach to hardware-in-the-loop testing
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Abstract
Flight testing of ballistic missile interceptors is limited by the complexity and costs of the test exercises, and inherent test limitations. While flight testing remains an essential part of ballistic missile weapons systems test programs, alternate test methods, such as hardware-in-the- loop (HWIL) testing, are used to fully characterize system operational characteristics. An integrated test approach that spans all levels of testing has been developed by the Ballistic Missile Defense Organization (BMDO) to characterize their developing and fielded weapon systems. The BMDO has developed an integrated three tiered HWIL testing concept to assess the performance of its acquisition programs. The three tiers are the element level which includes sub-element level testing of critical components, the weapon system level, and the family of systems (Fos) level. The objective of element level testing is to evaluate the performance of each element of the weapon system with emphasis on exercising the processing components of the element under test. Element level testing is focused on testing the internal interactions of each test element in a simulated environment. The objective of weapon system level is to evaluate the data exchange between the elements of the weapon system in an integrated, simulated operational environment. The primary purpose of FoS level testing is assessing the interoperability of ballistic missile defense (BMD) weapon systems, both under development and fielded. This paper examines the test processes and objectives which occur at each of the three HWIL tiers, describes facilities and testbeds BMDO is using to implement this approach, and discusses how data from each of the tiers is used to help address program flight test issues and reduce program risk.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chet A. DeCesaris Jr. and Paul J. Millner "Integrated three-tiered approach to hardware-in-the-loop testing", Proc. SPIE 3084, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing II, (15 July 1997); https://doi.org/10.1117/12.280949
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