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24 October 1997 VLSI architecture for variable-block-size motion estimation with luminance correction
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This paper describes the architecture and application of a flexible 100 GOPS (giga operations per second) exhaustive search segment matching VLSI architecture to support evolving motion estimation algorithms as well as block matching algorithms of established video coding standards. The architecture is based on a 32 by 32 processor element (PE) array and a 10240 byte on-chip search area RAM and allows concurrent calculation of motion vectors for 32 by 32, 16 by 16, 8 by 8 and 4 by 4 blocks and partial quadtrees (called segments) for a plus or minus 32 pel search range with 100% PE utilization. This architecture supports object based algorithms by excluding pixels outside of video objects from the segment matching process as well as advanced algorithms like variable block-size segment matching with luminance correction. The VLSI has been designed using VHDL synthesis and a 0.35 micrometer CMOS technology and will have a clock rate of 100 Mhz (min.) allowing the processing of 23668 32 by 32 blocks per second with a maximum of plus or minus 32 pel search area.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Peter M. Kuhn and Walter Stechele "VLSI architecture for variable-block-size motion estimation with luminance correction", Proc. SPIE 3162, Advanced Signal Processing: Algorithms, Architectures, and Implementations VII, (24 October 1997);

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