Architecture for web-based image processing

Vason P. Srini; David Pini; Matt D. Armstrong; Sayf H. Alalusi; John Thendean; Sain-Zee Ueng; David P. Bushong; Erek S. Borowski; Elaine Chao; Jan M. Rabaey

doi:10.1117/12.279606

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19 September 1997 Architecture for web-based image processing

Vason P. Srini, David Pini, Matt D. Armstrong, Sayf H. Alalusi, John Thendean, Sain-Zee Ueng, David P. Bushong, Erek S. Borowski, Elaine Chao, Jan M. Rabaey

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Proceedings Volume 3166, Parallel and Distributed Methods for Image Processing; (1997) https://doi.org/10.1117/12.279606
Event: Optical Science, Engineering and Instrumentation '97, 1997, San Diego, CA, United States

Abstract

A computer systems architecture for processing medical images and other data coming over the Web is proposed. The architecture comprises a Java engine for communicating images over the Internet, storing data in local memory, doing floating point calculations, and a coprocessor MIMD parallel DSP for doing fine-grained operations found in video, graphics, and image processing applications. The local memory is shared between the Java engine and the parallel DSP. Data coming from the Web is stored in the local memory. This approach avoids the frequent movement of image data between a host processor's memory and an image processor's memory, found in many image processing systems. A low-power and high performance parallel DSP architecture containing lots of processors interconnected by a segmented hierarchical network has been developed. The instruction set of the 16-bit processor supports video, graphics, and image processing calculations. Two's complement arithmetic, saturation arithmetic, and packed instructions are supported. Higher data precision such as 32-bit and 64-bit can be achieved by cascading processors. A VLSI chip implementation of the architecture containing 64 processors organized in 16 clusters and interconnected by a statically programmable hierarchical bus is in progress. The buses are segmentable by programming switches on the bus. The instruction memory of each processor has sixteen 40-bit words. Data streaming through the processor is manipulated by the instructions. Multiple operations can be performed in a single cycle in a processor. A low-power handshake protocol is used for synchronization between the sender and the receiver of data. Temporary storage for data and filter coefficients is provided in each chip. A 256 by 16 memory unit is included in each of the 16 clusters. The memory unit can be used as a delay line, FIFO, lookup table or random access memory. The architecture is scalable with technology. Portable multimedia terminals like U.C. Berkeley's InfoPad can be developed using the proposed parallel DSP architecture, color display, pen interface, and wireless network communication for use in clinics, hospitals, homes, offices, and factories.

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Vason P. Srini, David Pini, Matt D. Armstrong, Sayf H. Alalusi, John Thendean, Sain-Zee Ueng, David P. Bushong, Erek S. Borowski, Elaine Chao, and Jan M. Rabaey "Architecture for web-based image processing", Proc. SPIE 3166, Parallel and Distributed Methods for Image Processing, (19 September 1997); https://doi.org/10.1117/12.279606

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