30 October 1997 2D discrete wavelet-transform implementation in FPGA device for real-time image processing
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Abstract
A new approach to FPGA implementation of 2D discrete wavelet transform is presented. This architecture allow high accurate and sampling rate DWT realization based on FIR filters of substantial length to be implemented on current generation FPGAs. The scheme is based on two parallel pipelined linear phase 17-tap FIR filters with common shift register, partial adders and look-up tables as coefficient multipliers with 4-stage pipelined architecture. The transform is realized in three stages controlled by the state machine, where temporary (L and H) and final subimages (LL, LH, HL, and HH) are created. High throughput (1050 MIPS) and external memory controller allow efficiency concurrent cooperation with external processors.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Piotr Wasilewski, "2D discrete wavelet-transform implementation in FPGA device for real-time image processing", Proc. SPIE 3169, Wavelet Applications in Signal and Image Processing V, (30 October 1997); doi: 10.1117/12.279705; https://doi.org/10.1117/12.279705
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