14 August 1997 Resist profile and CD control improvement by using optimized resist thickness and substrate film stack ratio for 0.35-um logic process
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Proceedings Volume 3183, Microlithographic Techniques in IC Fabrication; (1997) https://doi.org/10.1117/12.280545
Event: ISMA '97 International Symposium on Microelectronics and Assembly, 1997, Singapore, Singapore
Abstract
LOCOS is the most widely used method for 0.35 micrometers process isolation. 2000 angstrom silicon nitride on 200 angstrom padoxide was selected as oxidation barrier before process optimization for the need of control the bird's beak and stress which affects the subsequent gate oxide quality. However, resist profile is prone to footing at this film stack. Severe footing could make minimum space CD too small, even not opened, to cause isolation failure. Experiment data shows that if nitride thickness varies from 1.9 K to 2.1 K, line CD variation can be up to 0.08 micrometers for a 0.6 micrometers line, which is about 80 percent of CD variation budget. Based on simulation results, 8 different nitride thickness in the range of 1750 angstrom to 2100 angstrom with step of 50 angstrom were deposited on 200 angstrom padoxide. Swing curve, CD versus nitride thickness for resist Emax and Emin, CD versus different exposure dose charts were obtained. Resist profile cross-sectional SEM pictures were also done to confirm simulation and in-line CD SEM measurement. An optimum combination of substrate film stack and resist thickness was selected. After implementation of this optimization, the sensitivity of CD to the nitride thickness was greatly reduced. Better resist profile and CD control were obtained. This was well confirmed by in-line monitoring data.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ming Hui Fan, Ming Hui Fan, Raymond Yu, Raymond Yu, Ronfu Chu, Ronfu Chu, Chet Ping Lim, Chet Ping Lim, } "Resist profile and CD control improvement by using optimized resist thickness and substrate film stack ratio for 0.35-um logic process", Proc. SPIE 3183, Microlithographic Techniques in IC Fabrication, (14 August 1997); doi: 10.1117/12.280545; https://doi.org/10.1117/12.280545
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