Space Processor Technology Tradeoffs

W. W. Crane; W. S. Chan; C. C. Huang

doi:10.1117/12.933164

4 August 1982 Space Processor Technology Tradeoffs

W. W. Crane, W. S. Chan, C. C. Huang

Proceedings Volume 0319, Very High Speed Integrated Circuit Technology for Electro-Optic Applications; (1982) https://doi.org/10.1117/12.933164
Event: 1982 Los Angeles Technical Symposium, 1982, Los Angeles, United States

Abstract

Computational requirements for proposed satellite surveillance missions have grown beyond the capabilities of existing space qualified computers. In fact, throughput for a space processor of the future is expected to be in excess of 50 million instructions per second (MIPS). This processing capability must be attained with minimum system size, weight and power. Recent studies indicate that a distributed processing system is a realistic method of attaining this goal. Complementary metal oxide semiconductor (CMOS) and very high speed integrated circuits (VHSIC) technologies were evaluated for the design of a modular, high throughput, space computer. Operational and physical property attributes considered include: 1) processing throughput versus system power, 2) local heat dissipation, 3) device radiation tolerance and 4) multiprocessor communication techniques. The conclusion of the evaluation makes a series of recommendations and suggests a set of tests to enable the space community to select the optimum technology and system architecture for a modular space processing system.

Citation Download Citation

W. W. Crane, W. S. Chan, and C. C. Huang "Space Processor Technology Tradeoffs", Proc. SPIE 0319, Very High Speed Integrated Circuit Technology for Electro-Optic Applications, (4 August 1982); https://doi.org/10.1117/12.933164

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