Charges stored in a memory cell of a dynamic random access memory are lost by the Shockley-Read-Hall (SRH) current that is generated at carrier traps in the space-charge-region (SCR) of a junction. Magnitude of the SRH current is determined by the trap levels that are distributed not only among cells, but also within a cell. This trap-level distribution causes the temperature-dependent variation in the data retention times. The SRH current is enhanced by an SCR field, and the distribution of the field among cells also increases the variation in the retention times. Variation in the number of traps, on the other hand, contributes only slightly to the retention-time distribution. From these results we find that reduction of the electric-field distribution, as well as of the average field, is important to improve the data-retention characteristics.

This paper presents a study of threshold voltage (V_th) fluctuation in n-MOSFETs having both gate lengths (L_g) and widths (W) as small as 0.15 micrometer for giga-bit DRAM cell transistors. The effects of varying L_g, W, and the gate oxide thickness (T_ox) and fluctuation in the concentration of channel impurities (N_a) were studied in detail. We fabricated and evaluated n-MOSFETs having various sizes of L_g and W. The V_th and the V_th fluctuation of these devices, when L_g/W equals 0.14/0.15 micrometer and the channel implantation condition was B⁺, 10 keV, and 9E12 cm^-2, were 0.33 V and 47 mV, respectively. A short- channel effect and a slight inverse narrow-width effect were also observed. By determining the origin of the V_th fluctuation, we found that the short- and narrow-channel effect (combined with variations in device dimensions) had only a minor effect on V_th fluctuations at higher channel impurity concentrations, and that the channel impurity fluctuation had the biggest influence. This channel impurity fluctuation cannot be explained simply by the statistical dopant fluctuation. We presume that anomalous impurity diffusion, such as transient enhanced diffusion (TED), during the gate oxidation process may be the dominant factor.

Small feature sizes and reduced tolerances of state-of-the-art microelectronic devices make them extremely sensitive to manufacturing variations. This paper describes two approaches dealing with manufacturing variations: process control and statistical design for manufacturability. Process control seeks to reduce the variability of each process module and statistical design seeks to minimize the impact of the variability. An example illustrates the use of process control to minimize variability. Then, a novel approach for statistical design and its application to statistical optimization of deep submicron CMOS is described. This approach is based on a Markov representation of a process flow that captures the sequential and stochastic nature of semiconductor manufacturing. Using this approach we have been able to predict the variability in device performance for a number of process flows. Transistor designs and process flows optimized using this approach show lower variation in key device performances on fabrication.

A methodology is presented for optimizing transistor performance by considering the coupled response of the on- state and off-state parameters of saturated drain current and subthreshold drain leakage current, respectively. Good die yield in a CMOS digital logic integrated circuit is shown to be highly correlated to a multiple linear model of these transistor performance parameters using empirical data. These currents are correspondingly highly correlated to threshold voltage and effective channel length. Monte Carlo simulation is used to predict the distributions of saturated drain current and subthreshold drain current based on the natural variation of threshold voltage and effective channel length. A case study is presented using this methodology for the development of a CMOS retrograde well process using high energy implants from a baseline process using conventional diffused wells.

A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.

CMOS scaling is requiring increased attention on several aspects of ultrathin oxides, including both physical and electrical properties. In particular, surface preparation and interface quality will play an increasingly important role as the gate oxide thickness is scaled down to below 30 angstroms for sub-0.1 micrometer devices. This means that standard thermal desorption of sacrificial oxides or even H-terminated surfaces will have to be closely investigated to determine if the requirements for interface roughness and uniformity can still be met, or whether new preparation techniques will have to be used. Growth of oxides in the ultrathin regime is also a concern because of uniformity and reproducibility problems using furnaces, including pinhole formation in films. Physical and electrical characterization of ultrathin oxides presents difficulties with most currently used techniques. Measurement of the oxide thickness below 30 angstrom involves substantial uncertainties in standard techniques such as spectroscopic ellipsometry form impurities and interface roughness and in C- V analysis from large tunneling currents and poly-depletion effects. One possibility for overcoming these problems is to use the direct tunneling current to determine the electrical thickness of the oxides. It is important to characterize the effect of decreasing oxide thickness in the ultrathin regime on fundamental parameters such as the electron effective mass m* and the band gap, especially for predicting the electrical behavior of these oxides. Boron penetration effects also present problems for device operation with the ultrathin oxides which need to be addressed. The combination of these concerns leads toward alternate gate dielectric materials with higher dielectric constants and higher resistance to B diffusion.

As voltages scale with device miniaturization, it is desirable to maintain dual-voltage operation for efficient system integration. While this dual-voltage approach is commonly used for CMOS EEPROM circuits, its use in an ASIC environment is relatively new. The effects of pre-gate clean processing technology on oxide integrity were investigated for both low (3.3 V) and high (5 V) voltage gate oxides in a 0.35 micrometer triple level metal CMOS process with dual gate oxide. Significant improvements in the high-voltage gate oxide quality were realized by reducing the temperature of the pre- gate SC1 (NH₄OH/H₂O₂/H₂O) cleaning solution and by minimizing the exposure time of the high-voltage gate oxide to HF. Also, addition of HCl to dilute HF as the final step in the pre-gate cleaning improved the high-voltage gate oxide quality. These improvements to the high-voltage gate oxide quality were achieved without compromising the quality of the low-voltage gate oxide.

We have developed a thin (35, 50 and 65 angstrom) gate oxidation process for Lucent's sub-0.25 micrometer technologies and their enhancement modules. These oxides have significantly improved quality (defect density < 0.3/cm², E_bd > 18 MV/cm, log N_bd > -0.3 C/cm² and D_it and O_f < 2 X 10¹⁰/cm²-eV) as a result of stacking and nitridation. Impacts of stacking and nitridation on leakage (D_o), breakdown (E_bd), wear-out (N_bd) and charge trapping behavior (D_it and Q_f) are more dramatic for thinner (35 and 50 angstrom) oxides where Si/SiO₂ interfacial sub-structure plays a dominant role. Stacked oxide generates a planar and stress-free interface due to stress modulation during densification/oxidation. These stress- budgeted oxides are more resistant to process/induced damage that causes variability in MOSFET parameters and degradation during hot-carrier and Fowler-Nordhaim stressing. Light nitrogen incorporation (less than 5%) improves thickness uniformity, charge-to-breakdown (N_bd) and endurance, nitrogen incorporation also reduces Si-H bonds by replacing with Si-N bonds resulting in a reduction traps and increased interface resistance to current stress.

In this paper, we study and compare dual-gate CMOS devices fabricated with various processes such as standard or NO- nitrided gate oxides, polycrystalline or amorphous silicon gates, boron or BF₂ implantation for p⁺-poly and S/D formation, and different drive-in conditions. It is found that NO nitridation of gate oxides can improve device performance for short channel PMOSFETs over control SiO₂. However, pile-up of boron in nitrided gate oxides may degrade gate oxide reliability in PMOS devices. Amorphous silicon gates can effectively prevent boron penetration into gate oxides at a cost of aggravated poly-depletion effects. When BF₂ implantation is used for p⁺-poly formation, fluorine improves the resistance of SiO₂/Si interfaces to hot-carrier stress but it enhances boron diffusion in gate oxides. The process optimization of dual-gate CMOS regarding device performance and hot-carrier reliability is systematically studied.

In this paper, the quasi-breakdown is demonstrated to be a dominant failure mechanism in ultra-thin dielectrics with thicknesses less than 50 angstrom and should be considered as a reliability issue to avoid overestimation of dielectric breakdown. Under high stress current density (-Vg), the charge to catastrophic breakdown decreases with decreasing the oxide thickness because of dielectric breakdown in the structural transition layer existing SiO₂/Si interface. But the Q_bd rapidly increases again with decreasing the oxide thickness below 50 angstroms under low stress current density due to the difficulty in building up electric field to cause catastrophic breakdown through the localized conduction path induced by the quasi-breakdown prior to catastrophic breakdown. The quasi-breakdown was suppressed in NO-annealed oxide.

This paper reviews and discusses a potential of Si-MOS rf technology, focusing on the fundamental rf characteristics, such as f_(tau ), fmax, noise, and linearity, also identical rf circuits, such as low noise amplifier, mixer, and oscillator.

The continued emergence of wireless applications as perhaps the most financially significant market in recent years, wireless technology has become a global core competency. The demand for increasingly higher rates of data transmission, low-power operation and high frequency operation will eventually require integration of nanoscale electronics into available silicon technologies. A broad application base is expected for co-integrated resonant tunneling/CMOS technology (termed QMOS for quantum metal oxide semiconductor) because of the expected factor of 5 to 10 increase in functional density and speed when compared to conventional all-CMOS high speed circuit approaches. These circuits are realized by integrating compound semiconductor resonant tunneling diodes and three terminal high frequency components with conventional CMOS circuitry through the use of thin-film integration processes. The focus of this work is to develop reliable, densely packed nanoelectronic interfaces to bring higher functionality to Si systems. We combine: (1) high performance, resonant tunneling electronics; (2) high frequency, wireless electronics; and (3) conventional CMOS electronics into a single wafer level integrated system.

This paper describes Si or SiGe selective epitaxial growth (SEG) technology for the application to LSI fabrication. SEG has become one of the promising technologies, because this process realizes the self-aligned and the low-temperature in- situ doping process. Several advanced device structures have been proposed utilizing the SEG process advantages. However, there have been left several problems to be resolved in order to introduce this advanced process into the LSI fabrication. Wafer surfaces can not escape from the damage or contamination through the practical LSI fabrication process. The facet control or the fillings in the complex device structures are required. Several novel techniques of the surface treatment and the SEG conditions are introduced to overcome these problems. Some successful examples of SEG application are demonstrated to the advanced device structures, such as elevated S/Ds in MOS-FETs, contact fillings in DRAMs, and SiGe epi-base formation in high speed bipolar transistors, by an ultra-high vacuum chemical vapor deposition (UHV-CVD) system. For realizing future high density and high performance devices, which will require increasingly complex fabrication process, SEG will become one of the break-through technologies to ensure simpler processing.

This paper will review growth of Si-Ge and Si-Ge-C alloys using various low thermal budget epitaxial schemes such as UHVCVD, RTPCVD and MBE. The growth issues, materials aspects and bandgap and strain engineering in these alloys will be discussed. The prospective of using these alloys in strained-channel Si-Ge MOSFETs and MODFETs in order to enhance CMOS in the giga-scale era will be discussed. We will also describe the use of these films in Si-Ge HBTs for high speed r-f type applications.

Strained-Si films show considerably higher electron mobility than conventional silicon films which results in increased transconductance and drive current of strained-Si channel NMOSFETs. However, in order to form tensile strained silicon it is necessary to use relaxed Si_1-xGe_x 'substrates,' typically requiring the growth of several microns of a graded Si_1-xGe_x layer, followed by a buffer layer. In this work, we have used ion implantation of Ge followed by high- temperature annealing to form a relaxed substrate, eliminating the growth of graded, relaxed layers, and simplifying the fabrication process. Upon this film, a 1000 angstrom buffer layer of Si_0.85Ge_0.15 was grown. X-ray analysis indicates that the films formed by this method are 75% relaxed. This was followed by a 200 angstrom thick strained-Si layer. For comparison, unstrained Si epitaxial films and a 2000 angstrom thick film of Si_0.85Ge_0.15 (on unimplanted Si) followed by 200 angstrom of Si were used. A typical self-aligned MOS process with modifications to achieve low-thermal budget was used to fabricate NMOSFETs with gate lengths ranging from 10 micrometer to 0.8 micrometer. Strained-Si devices show a 17.5% higher peak linear g_m than control devices as a result of higher electron mobility in the strained-Si channel.

Pre-amorphization scheme has been widely used to form shallow source/drain extension for deep sub-micron CMOS technology. In this paper, different Sb and In implantation conditions (various implant energies and doses) were used before BF₂ and As HDD implant to study their effects on pMOS and nMOS characteristics, respectively, such as L_gmin (the gate length at I_off equals InA/micrometers at V_g EQ 0, V_d equals 1.5 V), I_drive (drive current when V_g equals V_d equals 1.5 V), and diode leakage. These characteristics will also be compared with those obtained from devices without the pre-amorphization. TEOS 1st spacer in different thickness and various final RTA temperatures were also used to study their effect on the drive current. The key results are as follows: (1) A 4% improvement in I_drive(strong) (from 185 (mu) A/micrometers to 193 (mu) A/micrometers ; the drive current at I_off equals InA/micrometers at supplying voltage of 1.5 V and t_ox approximately equals 39 angstroms) and approximately 0.02 micrometers reduction in L_gmin (from approximately 0.16 micrometers to approximately 0.14 micrometers ) were observed for the pMOS devices with Sb pre-amorphization when the same thickness of the 1st spacer was used. These improvements are due to the formation of a more shallow and abrupt HDD when pre-amorphization is used. (2) With the requirements of L_gmin equals approximately 0.16 micrometers , a p-channel I_drive(strong) equals 211 (mu) A/micrometers at L_gmin equals approximately 0.16 micrometers were obtained with a thin 1st spacer and with Sb pre-amorphization in this study. For the same L_gmin requirement, a thick 1st spacer (150 angstroms thicker than the thin one) had to be used for a device without the pre-amorphization, which resulted in a higher R_sd and thus degraded the drive current to I_drive(strong) equals 185 (mu) A/micrometers . (3) The Sb implant conditions do not form an effective pocket implant doping for either case studied. A similar improvement in L_gmin is observed for different annealing temperatures studied. (4) In contrast to the L_gmin of a pMOS, the junction diode leakage is sensitive to the Sb implant condition. The diode leakage increases with Sb implant energy and dose. (5) Contrary to the Sb pre- amorphization cases, no significant improvement in either I_drive and L_gmin is observed in the nMOS devices with In pre-amorphization.

We have examined low energy BCl₂ and BBr₂ implants as a means of fabricating ultra-shallow P⁺-N junctions. Five keV and 9 keV BCl₂ implants and 18 keV BBr₂ implants have been compared to 5 keV BF₂ implants to study the benefits of using these species. BCl₂ and BBr₂, being heavier species, have a lower projected range and produce more damage. The greater damage restricts channeling, resulting in shallower as-implanted profiles. The increased damage amorphizes the substrate at low implant doses which results in reduced transient enhanced diffusion (TED) during the post-implant anneal. Post-anneal SIMS profiles indicate a junction depth reduction of over 10 nm (at 5 X 10¹⁷ cm^-3 background doping) for 5 keV BCl₂ implants as compared to 5 keV BF₂ implants. Annealed junctions as shallow as 10 nm have been obtained from the 18 keV BBr₂ implants. The increased damage degrades the electrical properties of these junctions by enhancing the leakage current densities. BCl₂ implanted junctions have leakage current densities of approximately 1 (mu) A/cm² as compared to 10 nA/cm² for the BF₂ implants. BBr₂ implants have a lower leakage density of approximately 50 nA/cm². Low energy BBr₂ implants offer an exciting alternative for fabricating low leakage, ultra-shallow P⁺-N junctions.

In this paper, key issues of salicide process are studied for a variety of additional nitrogen (N) implantation step. As devices are scaled down to deep sub-micron level, transformation of TiSi2 from the high resistivity metastable C49-phase to fmal C54-phase is retarded. Different techniques had been developed to enhance the silicidation process, including PAT (pre-amorphization implant) to enhance C54-phase TiSi2 nucleation, and ITM (Jmplant through metal) to iniroduce Ti/Si interface-mixing. It is of great interest to thrther improve the process such that the use of self-aligned TiSi2 process can be further extended down to deep sub-micron devices without switching to other materials. Impact of incorporating N implantation into the conventional self-aligned TiSi2 sub-micron CMOS devices is presented. Silicidation reaction is found to be enhanced by N implantation. As a result, lower sheet resistance is achieved on narrow polysilicon line. Low energy and dosage ion-implantation conditions are preferred in order to minimise the gate to source/drain leakage. p+ and n+ junction leakage will be further discussed in this article. This is the very first study on the effect of N ion-implantation on silicidation reaction. SEM and AFM were used to study the impact of N incorporation, cross-section TEM were perfonned to study the defects generated after N implantation. Keywords: N ion-implantation, RTA, TiSi2, sheet resistance, gate to source/drain leakage, junction leakage, salicide process, defects

MOSFETs with partially contacted source/drain regions are often used in ASIC designs in order to improve the layout density of the gate arrays. Such contacting scheme adds resistance to current flow which reduces transistor current and hence degrades device performance. This paper presents the effect of source/drain region sheet resistance on the performance figure of merit (FOM) for partially contacted deep submicron CMOS transistors. These partially contacted transistors are modeled as distributed network of MOSFETs and resistances in order to study the impact of source/drain region resistance on drive currents. It is found that the source/drain sheet resistance plays a significant role in determining the FOM of these transistors. For example, our modeling shows that for 0.11 micrometer technology, a source/drain region sheet resistance of only 7 Ohms/sq. results in 1% degradation in performance FOM for diagonally contacted transistors with W/L of 20 and W_s of 0.27 micrometer.

Self-aligned contacts (SAC) have been successfully scaled down to 0.2 tm, for high speed SRAM fabrication at the 64Mb density level. All factors affecting SAC contact resistance (Re) are investigated in depth to reduce the overall resistance of SACs. For a 0.25x0.45 im2 poly/n contact a contact resistance of 65 (1 =8 has been obtained. The factors which allow SACs to enable fabrication technologies at and below the 0.25 im size scale, are discussed.

Low power advantage of SOI (silicon-on-insulator) technology is presented. A 0.5 V operation ALU is demonstrated by employing a gate-to-body connected structure. From the viewpoint of reliability in process integration, origin of a leakage current between source and drain is investigated in detail. The performance advantage of fabricated SOI ALUs over bulk devices as well as issues to be overcome are discussed.

Results are reported on the high-frequency characteristics of low threshold MOSFET in an LNA (low noise amplifier) for 900 MHz applications. It is shown that an excellent noise figure N_F of 1.2 dB, together with good input related IP₃ equals 11 dBm and power gain A_p equals 13 dB, can be obtained in a 3.3 V CMOS 0.6 micrometer process. NF_min showed to be constant over a wide current range, making it possible to achieve optimum total LNA performance.

This paper describes a detailed design analysis that has been performed in order to identify the optimum design parameter regions for 0.18 micrometer NMOSFET devices for low power applications. The objective of the analysis was to obtain the highest possible drive current while satisfying a target off- state leakage criterion and a short-channel constraint for a supply voltage of 0.9 V. In the analysis, a set of basic structural and doping profile parameters was utilized in light of the anticipated future trends for this technology generation. In order to control adverse short-channel characteristics for these very short L_eff devices and achieve the largest possible drive current, channel profile engineering was required. Two different channel engineering options, a boron halo implant and a boron anti-punchthrough (APT) implant were investigated. The peak doping (dose) and peak depth (energy) of these implants were varied in order to analyze the effects on device performance. For each selected halo or APT dose and energy, the saturation drain current, I_Dsat, and the change in threshold voltage, (Delta) V_T, due to drain-induced-barrier-lowering (DIBL) were monitored. A design matrix was generated for devices at each of a number of different shallow S/D junction depths, showing both the I_Dsat and (Delta) V_T (DIBL) values plotted against the halo or APT implant dose and energy. These design matrices provide an understanding of the acceptable regions of device operation for different profile conditions. Finally, a comparison of the use of a halo implant versus an APT implant is discussed for this low-power technology.

Predictive device simulation is essential in order to improve MOSFET design, and reduce development time and costs. In this paper, the results of a simulation study carried out to predict the performance of N and P channel MOSFETs having a physical gate length of 0.10 micrometer at supply voltages of 1.2 and 1.5 V are presented. The study was used to determine the feasibility of the FOM goal for scaled 0.10 micrometer CMOS, and to identify the values of key device parameters [the external source drain resistance (Rext), poly-gate doping, etc.] which would improve device performance.

Single N+ polycide gate CMOS process has been scaled to the sub-0.2 micrometer gate-length regime. Estimated worst-case hot-carrier effect was 7% degradation in N-IDSAT for 10 years of continuous operation at 2.8 V. Being a buried channel device, P-MOSFETs presents a trade-off between VT adjustment and CD margin. It was manifested by the gate-to-drain overlap which increases as VT becomes less negative with more channel implant doses. We found that the relationship between gate-to- drain overlap and PMOS VT was almost independent of the n-well doping and source/drain junction depth. This indicates that the buried channel of P-MOSFETs acts as an extension to the source/drain. For VT equals 0.5 V, gate-to-drain overlap was 0.04 micrometer, and the n-well doping was twice of p-well doping for the same gate length, in order to account for the shorter effective channel length.

The impact of photoresist taper and implant tilt angle on the interwell isolation of a sub-0.25 micrometer CMOS technology is investigated. It is shown that as the trench depth is decreased and the n-well dose and energy is increased, interwell isolation below 1 micron N⁺/P⁺ spacing is degraded. The reduction of photoresist taper is shown to be a key factor in improving interwell isolation and decreasing MOSFET device parasitics. By optimizing the photoresist process to minimize taper, acceptable N⁺/P⁺ isolation is achieved down to 0.7 micrometers. Also, by utilizing a two dimensional interwell isolation test structure, it is found for the first time that as the interwell isolation is scaled into the sub-micron regime, lateral n-well dopant displacement caused by the implant tilt angle can result in reduced overlay margin.

Dielectric film thickness variation arising from layout pattern dependency remains a major concern in oxide CMP. The severity of the pattern density effect is a function of the die location on the wafer, thus a combined wafer/die pattern dependent polishing model is required to fully assess the effectiveness of the process for a given planarization requirement. In this work, a two stage modeling methodology which accounts for both wafer-scale variation and within-die pattern dependencies, as well as their interaction, is developed. The effectiveness of the methodology is demonstrated over a range of polishing process conditions and consumable choices. We find that the integrated wafer/die CMP model accurately predicts the resulting increase or decrease in die-level pattern dependencies as a function of die position on the wafer.

One of the major problems for SOI technologies with LOCOS- based isolation is the high subthreshold leakage current along the field edge of NMOS devices. Partially depleted SOI transistors with a modified poly-buffered LOCOS isolation show a high off-leakage for devices with a silicon thickness of 900 angstroms and a gate oxide thickness of 105 angstroms due to the low threshold voltage of the parasitic edge device. The off-leakage is reduced by two orders of magnitude by increasing the doping of the edge device by using either a retrograde well or a lower temperature ILD0 reflow cycle. A further improvement in the off-leakage is observed by thinning the gate oxide thickness to 90 angstroms while increasing the channel doping to maintain a similar threshold voltage. The edge device is also shown to be very sensitive to the silicon film thickness. For the same channel implants and gate oxide thickness, an increase in the silicon thickness from 900 to 1100 angstroms eliminates the edge device resulting in excellent subthreshold characteristics.

Severe hot-carrier-induced device lifetime degradation has been observed on deep submicron N-MOSFETs after they are processed through the backend for multi-layer-metal interconnect. Our experimental data show that the hot-carrier lifetime degradation is dependent on: (1) H₂ annealing/sintering time; (2) choice of inter-metal-dielectric process, i.e., spin-on-glass (SOG) or high-density-plasma chemical-vapor-deposition (HDP-CVD) process; and (3) choice of pre-metal-dielectric process, i.e., BPSG (borophosphosilicate glass) or BPTEOS/O₃ (borophosphosilicate-tetra-ethoxy- silane and ozone oxide) deposition. The device hot-carrier lifetime can degrade more than 50% due to prolonged H₂ sintering time, and it could easily degrade by a order of magnitude when HDP-CVD oxide, instead of SOG, is used for inter-metal dielectric deposition. The gate oxide always remains of excellent quality through the entire backend processing, which indicate that the degradation is not caused by plasma damage to the gate oxide but by hydrogen-related defects at the Si-SiO₂ interface instead.

Routine use of an etch-stop layer during semiconductor processing favors circuit density and performance through the use of local interconnect and similar damascene processes, and also allows the use of manufacturable etch recipes. Previous studies have demonstrated that post transistor definition, topside passivation and deposition techniques can significantly impact device degradation characteristics. This work further investigates the choice of local interconnect etch-stop layer and its effect on channel hot-electron degradation. A reduction in channel hot-electron degradation is demonstrated through the use of N₂O anneal gate oxide, and using experimental data a possible degradation mechanism, caused by the presence of the etch-stop layer, is identified. A brief review of the compatibility of etch-stop layers with high performance 0.3 micrometer CMOS devices is presented through interface state and hot-electron stress measurements.

This paper reports plasma-induced charging damage in p⁺-polysilicon PMOSFETs as a function of amount of boron penetration. Plasma charging effect is amplified using contact antenna structures with ratios of 10, 100 and 1 K. The antenna is connected to the gate of a 25 micrometer/0.8 micrometer PMOSFET from a matched pair to minimized device performance deviation due to process non-uniformity. It is found that initial device characteristics, such as threshold voltage, transconductance and subthreshold swing, are degraded in the antenna devices as compared to the control devices and this degradation is aggravated with the amount of boron penetration. The percentage degradation in maximum transconductance of the antenna devices is proportional to its increase in peak charge pumping current, suggesting that the degraded interface property is responsible for the reduced G_m. It is believed that boron-penetration causes latent defects in gate oxides and thereby increases charge trapping and interface states generation during stress, resulting in an enhancement of plasma damages in the p⁺-polysilicon PMOSFETs.

As CMOS technology is scaled to sub-0.18 micrometer gate lengths with gate dielectric thickness (t_ox) less than 40 angstrom, gate depletion effects becomes increasingly pronounced, which can lead to degradation in drive current, unless the gate electrode is heavily doped. For pMOS devices, high (boron) gate doping can lead to B penetration to the substrate resulting in threshold voltage shifts or non- uniformity as well as gate oxide reliability degradation. It has been widely reported that B penetration can be reduced by nitridation of the gate oxide as well as by reduction of subsequent thermal budgets especially in a hydrogen ambient, in which CVD nitride (commonly used as the spacer material for CMOS) deposition is performed. In this paper, we explore the effects of varying nitride spacer deposition process and time on B penetration for pMOSFETs with and without pre-etch gate B implant. Specifically, we compare a batch furnace LPCVD nitride deposition process at 700 degrees Celsius for 90 - 180 minutes with a single-wafer rapid-thermal CVD (RTCVD) process at 750 degrees Celsius for 4 - 6 minutes to form the same range of spacer thickness. Deposition temperature and time is chosen to allow appropriate throughput for each process. Device characteristics of a 0.18 micrometer CMOS implementation with 34 angstroms N₂O gate dielectrics are compared. Key results are the following. In this study, the 750 degree Celsius RTCVD nitride deposition leads to increased B penetration for pMOSFETs when compared to the 700 degree Celsius LPCVD process. In particular, for pMOSFETs with pre- gate B implant, it is observed that a 1000 angstrom RTCVD nitride deposition leads to a slightly larger Vt shift (24 mV, Vt shifts obtained from devices with/without pre-etch gate implant while maintaining the same total gate dose) compared to a 1000 angstrom LPCVD nitride deposition process (5 mV). Thinner RTCVD nitrides of thickness 700 angstrom lead to reduced Vt shift from 24 mV to 13 mV, which is still larger than the Vt shift of the 1000 angstrom LPCVD nitride layer, even though the RTCVD deposition time is less than 5 minutes. Although temperature of deposition may play a thermal activation role in the above results, it is additionally observed that the presence of the RTCVD nitride spacer can result in higher Vt shift even for devices with no pre-gate B implant. Specifically, it is found that with a S/D anneal of 1050 degrees Celsius (following deep S/D implantation), devices with a RTCVD nitride spacer show a lower Vt (larger Vt shift of 16 mV) than devices with an LPCVD nitride spacer of the same thickness. It is thus proposed that 750 degrees Celsius RTCVD nitride spacers can result in higher hydrogen content in the gate dielectric during anneal and/or deposition which can enhance B penetration with B from S/D implant. This property of the current RTCVD deposition process limits the process space (S/D dose and anneal temperature, time) for forming low boron penetration pMOS devices. However, it is found that other than B penetration, I_strong, L_gmin, R_sd, subthreshold swing as well as the effective electron and hole mobility are comparable or only slightly different between the RTCVD and LPCVD nitride spacers. NMOS also show comparable I_strong between the RTCVD and LPCVD nitride spacers. These observations lead to the conclusion that RTCVD nitride spacer process is applicable to sub-0.18 micrometer CMOS technologies.

Boron segregation toward implanted arsenic profile in Si during annealing was investigated under various annealing conditions. It is found that both the implant damage created by the arsenic implantation and arsenic deactivation enhance the diffusion of the embedded boron layer toward the shallow As implanted profile. This phenomena was found in both 650 degree Celsius furnace annealed (FA) and 1000 degree Celsius rapid thermally annealed (RTA) samples. For the 650 degree Celsius FA sample, the boron segregation peak was found located at the junction formed by implanted As, where residual dislocation loops at the original amorphous/crystalline (A/C) interface was also observed. However, no A/C interface dislocation loops were found to be present for the RTA samples. Additional anomalous boron segregation was observed for the 1000 degree Celsius RTA plus 750 degree Celsius FA samples. The additional boron segregation is not correlated with defect layers. It is, therefore, concluded that the anomalous boron segregation is caused by the electric field resulting from the formation of p-n junction.

In this paper, the effects of implanting nitrogen ions (N⁺) into the channel and source/drain/poly-silicon gate (poly-Si) regions on transistor characteristics are investigated. It was found that the use of N⁺ implantation into the channel reduces the reverse short channel effects (RSCE) tremendously. However, threshold voltage shifts of both n-ch an p-ch devices were observed. The thinning of the field oxide due to the extra N⁺ implantation was also seen. We attribute these threshold voltage shifts to the partial activation of the implanted nitrogen ions. When N⁺ were implanted into the source/drain/poly-Si regions, it was found that the roll-off of the n-ch devices and p+/n-well junction leakage current was degraded. We propose that these are due to the thinning of the field oxide at the bird's beak and to the partial activation of the implanted N⁺. It was found that there was no degradation in the n+/p-well junction leakage current which is consistent with the proposed mechanism.

This paper describes device simulation using a simulator (MEDICI) which is tuned to accurately predict the I-V characteristics of MOSFETS with conventional (non-pocket) channel profiles or pocket implants, and physical gate lengths from 10 micrometer to 0.16 micrometer. The key features of the simulation are, (1) the addition of a doping profile correction to the channel in NMOSFETs to model the inverse (reverse) short channel effect (ISCE/RSCE), (2) the incorporation of a new model to describe the pocket implant profile, and (3) the use of a two-step doping profile in the polysilicon gate to model gate depletion. The estimation of parameters for the profile correction and the pocket implant model, and the procedure of matching the simulated and experimental threshold voltage (V_T) as a function of gate length is described for the first time in this paper. The two- step gate doping profile, mobility parameters, external source-drain resistance R_sd and saturation velocity V_sat, used in the simulation, are determined by comparing the experimental and simulated C-V and I-V characteristics using the methodology discussed in reference 4. Good agreement between measured and simulated device characteristics is demonstrated for NMOS and PMOS devices with conventional profiles and pocket implants with varying doses, at supply voltages of 1 and 1.5 V.

A new computationally efficient ion implantation damage model has been developed and implemented in UT-MARLOWE Version 4.0. Based on the modified Kinchin-Pease formula, this model accounts for damage generation, damage accumulation, defect encounters and amorphization. With two parameters, one species-independent and the other species-dependent, good agreement with experimental impurity profiles has been obtained for sufficiently low energy implants. In addition, the amorphous layer thicknesses obtained in this model are also in reasonable agreement with experimental measurements. For higher energy implants, another parameter is introduced into the model to remedy a deficiency of the conventional Kinchin-Pease model. With this modification, good agreement with experimentally measured impurity profiles has been obtained for implant energies up to 65 keV for BF₂, 80 keV for boron, 180 keV for arsenic and phosphorus over a wide range of doses (1 X 10¹³ cm^-2 to 8 X 10¹⁵ cm^-2) and tilt angles and rotation angles. In combination with other CPU time reduction techniques, a speed improvement of up to an order of magnitude has been observed.

As channel lengths shrink continuously to smaller dimensions in order to improve performance and packing density, lithography, isolation, power supply and short channel effects have proved to be major limitations. Recently vertical MOSFETs (VMOS), also known as surround gate transistors, or 3-D side- wall transistors have been shown to overcome these process limitations. In this paper, we review the various VMOS technologies and applications and compare the performance of these devices to planar devices. We also present a novel deep submicron vertical SiGe/Si PMOSFET fabricated by Ge implantation. The Ge was implanted in the Si vertical channel to form a strained SiGe layer to increase drive current in P channel devices. PMOS drive current can be increased by about 100% compared to Si control devices. Thus, this technology offers CMOS circuit designers the flexibility to match PMOS and NMOS current drive capabilities, which was previously limited by the difference in electron and hole mobilities in Si.

It has been recently observed that ion implantation simulators based on the binary collision approximation (BCA) are not as accurate for low energy implants (less than 5 keV), despite their success at higher energies. The accuracy of molecular dynamics based simulators on the other hand, is independent of the implantation energy, but the computation times are extremely long. This work presents a low energy ion implantation model designed to bridge the gap between the rigorous but slow molecular-dynamics ion implantation simulators, and the less rigorous but computationally efficient binary collision approximation simulators, such as UT-MARLOWE. The deficiencies of the BCA at low energies are identified, and methods of overcoming them are discussed. The asymptotic collision approximation is abandoned in favor of a more rigorous calculation, and an improved multi-body collision algorithm that makes use of approximate multi-body potentials is introduced. The model is designed with computational efficiency in mind, and is in fact faster than conventional BCA simulators. The predictions of the low-energy model are found to be in very good agreement with molecular dynamics data, and a significant improvement over BCA predictions is observed. Finally, future improvements to the model are discussed.

Strain-compensated Si_1-x-yGe_xC_y alloy appears attractive because it may eliminate the constraints in Si_{1- x}Ge_x device design involving high Ge concentrations, thicker active layers, and may allow relatively higher process temperature windows. PMOSFET devices were fabricated with partially strained Si_1-x-yGe_xC_y films with Ge-to-C ratio of 30:1 in order to preserve the valence band offset to confine holes. Bulk and epitaxial Si, Si_1-xGe_x and completley strain-compensated Si_1-x-yGe_xC_y were also processed for comparison. An n⁺-poly gate PMOS process was used. The dc characteristics of the Si_{1-x- y}Ge_xC_y PMOSFETs with channel lengths varying from 0.8 to 10 micrometer were evaluated between room temperature and 77 degrees Kelvin and were compared to those of Si and Si_1-xGe_x PMOSFETs. The low field effective mobility in Si_1-x-yGe_xC_y devices were found to be higher than that of Si_1-xGe_x and Si devices at low gate bias and room temperature as a result of partial strain compensation. However, with increasing transverse fields and with decreasing temperatures, Si_1-x-yGe_xC_y, we observed degradation in device performance. This enhancement at low gate bias was attributed to the strain stabilization effect of C. At higher C concentrations, degraded performance was observed. This first application of Si_1-x-yGe_xC_y in PMOSFETs demonstrates potential benefits in the use of C with the column IV heterostructure system.

The characteristics of BST thin films prepared on Pt/SiO₂/Si substrates by MOCVD were investigated. The films were deposited with various flow ratios and temperatures. The dielectric constant ((epsilon) _r) was found to initially increase with increasing Ba/(Ba+Sr) flow ratio, reach to the maximum value ((epsilon) _r equals 184) at the flow ratio of 0.3, and then rapidly decrease with further increasing the flow ratio. No crystalline BST peak was observed in the films deposited with lower flow ratio than 0.3, while secondary BaCO₃ peaks were observed in those with higher flow ratio. It indicates that why maximum (epsilon) _r was achieved in the films with intermediate flow ratio. The BaCO₃ phase was disappeared in the BST films with the increase of deposition temperature. A two-step deposition method was proposed to improve (epsilon) _r (equals195) as well as surface morphology. However, it degraded leakage current of the films due to increased grain boundary area. Post annealing in O₂ ambient could reduce the leakage current, although an excessive oxidation reduced (epsilon) _r.

Flash memory devices, using reoxidized nitrided oxide (ONO) as the interpoly dielectric, have shown rapid degradation in performance under positive and negative constant current- stressing, especially so for the latter case. It is essential and of great urgency to improve the breakdown time (t_bd) of the dielectric layer for the application of programming and erasing of flash memory devices. The average dielectric breakdown time of a standard flash test stack, upon a 1 (mu) A positive constant current-stress, is about 50 seconds. Possible causes for the poor performance of the devices under such current stresses, are the rough surface of the bottom polysilicon layer, trapped fluoride ions at the interfaces within the ONO layer and the changes in the occupancy of the interfacial states at the interfaces between the polysilicon layers and the oxides. In this work, we reported the t_bds of a type of test stack, that were fabricated in two ways: some tests stacks were defined using the normal (standard) etch process flow (Stack X) while the others had numerous extended overetch (OE) process flow (Stack Z). The latter stacks recorded a higher average t_bd value under positive constant current-stressed. Therefore, this work suggested that slight extension of OE duration can be used to improve the t_bd of the memory devices under current-stressing.

In this paper, the polymer composition generated by three different combinations of gas chemistries for oxide etch are studied and the effects of different O₂ plasma strip duration on polymer removal are also presented. The etch chemistries used were CHF₃/CF₄, CO/CF₄/CHF₃ and C₄F₈/CO/CHF₃ chemistry. From the x-ray photoelectron spectroscopy (XPS) C 1s spectra, five distinct peaks are identified which correspond to C-C, C-CF_x, CF, CF₂, and CF₃. The C/F ratio is found to be highest for polymer generated by the C₄F₈/CO/CHF₃ chemistry, about 0.8, whereas the C/F ratios for those by CHF₃/CF₄ and CO/CF₄/CHF₃ chemistries are about 0.6. Atomic force microscopy (AFM) images show that the polymer generated by the C₄F₈/CO/CHF₃ chemistry is much rougher than that by CHF₃/CF₄ and CO/CF₄/CHF₃ chemistries. The XPS spectra of C 1s also show a significant decrease in the intensity of the more fluorinated carbon peaks (CF₃ and CF₂) after O₂ plasma strip. The C/F ratios increased to about 1.4 to 1.8 after O₂ plasma strip. The spectra are similar for different O₂ strip times, indicating the decrease is independent of O₂ strip duration. From the AFM images, all the polymers formed by CHF₃/CF₄ and CO/CF₄/CHF₃ chemistries are rather smooth with no visible change after O₂ strip. However, the polymers generated by C₄F₈/CO/CHF₃ chemistry are flattened with increasing O₂ strip duration. The high energy ion bombardment of oxygen ions probably have flattened the rough polymer surface.

A method for the compensation of the narrow-width effect of local oxidation and the self-adjustment of the narrow-channel transistor threshold voltage is proposed. The method enables the significant improvement of the device characteristics and isolation performance.

In this paper, we discuss scaled silicon bipolar transistor performance for advanced BiCMOS SRAM applications. In particular, we present experimental results of non-self aligned, single poly emitter bipolar transistors with critical dimensions scaled vertically and laterally. We demonstrate the device performance enhancement by properly scaling and show device design tradeoffs with key bipolar device parameters.