Paper
27 August 1997 Advantages of SOI technology in low-voltage ULSIs
Makoto Yoshimi, Shigeru Kawanaka, Takashi Yamada, Mamoru Terauchi, Tomoaki Shino, Toshiaki Fuse, Yukito Oowaki, Shigeyoshi Watanabe
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Abstract
Low power advantage of SOI (silicon-on-insulator) technology is presented. A 0.5 V operation ALU is demonstrated by employing a gate-to-body connected structure. From the viewpoint of reliability in process integration, origin of a leakage current between source and drain is investigated in detail. The performance advantage of fabricated SOI ALUs over bulk devices as well as issues to be overcome are discussed.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Makoto Yoshimi, Shigeru Kawanaka, Takashi Yamada, Mamoru Terauchi, Tomoaki Shino, Toshiaki Fuse, Yukito Oowaki, and Shigeyoshi Watanabe "Advantages of SOI technology in low-voltage ULSIs", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284591
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KEYWORDS
Field effect transistors

Scattering

Oxidation

Oxides

Reliability

Germanium

Silicon

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