As CMOS technology is scaled to sub-0.18 micrometer gate lengths with gate dielectric thickness (tox) less than 40 angstrom, gate depletion effects becomes increasingly pronounced, which can lead to degradation in drive current, unless the gate electrode is heavily doped. For pMOS devices, high (boron) gate doping can lead to B penetration to the substrate resulting in threshold voltage shifts or non- uniformity as well as gate oxide reliability degradation. It has been widely reported that B penetration can be reduced by nitridation of the gate oxide as well as by reduction of subsequent thermal budgets especially in a hydrogen ambient, in which CVD nitride (commonly used as the spacer material for CMOS) deposition is performed. In this paper, we explore the effects of varying nitride spacer deposition process and time on B penetration for pMOSFETs with and without pre-etch gate B implant. Specifically, we compare a batch furnace LPCVD nitride deposition process at 700 degrees Celsius for 90 - 180 minutes with a single-wafer rapid-thermal CVD (RTCVD) process at 750 degrees Celsius for 4 - 6 minutes to form the same range of spacer thickness. Deposition temperature and time is chosen to allow appropriate throughput for each process. Device characteristics of a 0.18 micrometer CMOS implementation with 34 angstroms N2O gate dielectrics are compared. Key results are the following. In this study, the 750 degree Celsius RTCVD nitride deposition leads to increased B penetration for pMOSFETs when compared to the 700 degree Celsius LPCVD process. In particular, for pMOSFETs with pre- gate B implant, it is observed that a 1000 angstrom RTCVD nitride deposition leads to a slightly larger Vt shift (24 mV, Vt shifts obtained from devices with/without pre-etch gate implant while maintaining the same total gate dose) compared to a 1000 angstrom LPCVD nitride deposition process (5 mV). Thinner RTCVD nitrides of thickness 700 angstrom lead to reduced Vt shift from 24 mV to 13 mV, which is still larger than the Vt shift of the 1000 angstrom LPCVD nitride layer, even though the RTCVD deposition time is less than 5 minutes. Although temperature of deposition may play a thermal activation role in the above results, it is additionally observed that the presence of the RTCVD nitride spacer can result in higher Vt shift even for devices with no pre-gate B implant. Specifically, it is found that with a S/D anneal of 1050 degrees Celsius (following deep S/D implantation), devices with a RTCVD nitride spacer show a lower Vt (larger Vt shift of 16 mV) than devices with an LPCVD nitride spacer of the same thickness. It is thus proposed that 750 degrees Celsius RTCVD nitride spacers can result in higher hydrogen content in the gate dielectric during anneal and/or deposition which can enhance B penetration with B from S/D implant. This property of the current RTCVD deposition process limits the process space (S/D dose and anneal temperature, time) for forming low boron penetration pMOS devices. However, it is found that other than B penetration, Istrong, Lgmin, Rsd, subthreshold swing as well as the effective electron and hole mobility are comparable or only slightly different between the RTCVD and LPCVD nitride spacers. NMOS also show comparable Istrong between the RTCVD and LPCVD nitride spacers. These observations lead to the conclusion that RTCVD nitride spacer process is applicable to sub-0.18 micrometer CMOS technologies.