27 August 1997 Device performance and optimization for 5th- and 6th-generation microprocessors
Author Affiliations +
Abstract
A family of CMOS processing technologies used to produce AMDs fifth and sixth generation microprocessors (K5 and K6) is described. Some of the issues that arose during the technology development and the transfer to manufacturing are also presented. Transistor performance is compared to literature results and shown to be best in its class.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bijnan Bandyopadhyay, Jon Cheek, Robert Dawson, Michael Duane, Jim Fulford, Mark I. Gardner, Fred N. Hause, Bernard Ho, Daniel Kadoch, Raymond Lee, Ming-Yin Hao, Chuck May, Mark Michael, Brad Moore, Deepak Nayak, John L. Nistler, Dirk Wristers, "Device performance and optimization for 5th- and 6th-generation microprocessors", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284617; https://doi.org/10.1117/12.284617
PROCEEDINGS
7 PAGES


SHARE
RELATED CONTENT


Back to Top