Effect of local interconnect etch-stop layer on channel hot-electron degradation

Jon Cheek; Homi E. Nariman; Dirk Wristers; Deepak Nayak; Ming-Yin Hao

doi:10.1117/12.284601

27 August 1997 Effect of local interconnect etch-stop layer on channel hot-electron degradation

Jon Cheek, Homi E. Nariman, Dirk Wristers, Deepak Nayak, Ming-Yin Hao

Proceedings Volume 3212, Microelectronic Device Technology; (1997) https://doi.org/10.1117/12.284601
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

Routine use of an etch-stop layer during semiconductor processing favors circuit density and performance through the use of local interconnect and similar damascene processes, and also allows the use of manufacturable etch recipes. Previous studies have demonstrated that post transistor definition, topside passivation and deposition techniques can significantly impact device degradation characteristics. This work further investigates the choice of local interconnect etch-stop layer and its effect on channel hot-electron degradation. A reduction in channel hot-electron degradation is demonstrated through the use of N₂O anneal gate oxide, and using experimental data a possible degradation mechanism, caused by the presence of the etch-stop layer, is identified. A brief review of the compatibility of etch-stop layers with high performance 0.3 micrometer CMOS devices is presented through interface state and hot-electron stress measurements.

Citation Download Citation

Jon Cheek, Homi E. Nariman, Dirk Wristers, Deepak Nayak, and Ming-Yin Hao "Effect of local interconnect etch-stop layer on channel hot-electron degradation", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284601

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