Paper
27 August 1997 Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies
Percy V. Gilbert, John Grant, Paul Tsui, Charles Fredrick King, William J. Taylor, Karl Wimmer
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Abstract
The impact of photoresist taper and implant tilt angle on the interwell isolation of a sub-0.25 micrometer CMOS technology is investigated. It is shown that as the trench depth is decreased and the n-well dose and energy is increased, interwell isolation below 1 micron N+/P+ spacing is degraded. The reduction of photoresist taper is shown to be a key factor in improving interwell isolation and decreasing MOSFET device parasitics. By optimizing the photoresist process to minimize taper, acceptable N+/P+ isolation is achieved down to 0.7 micrometers. Also, by utilizing a two dimensional interwell isolation test structure, it is found for the first time that as the interwell isolation is scaled into the sub-micron regime, lateral n-well dopant displacement caused by the implant tilt angle can result in reduced overlay margin.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Percy V. Gilbert, John Grant, Paul Tsui, Charles Fredrick King, William J. Taylor, and Karl Wimmer "Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284596
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Cited by 2 scholarly publications.
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KEYWORDS
Photoresist materials

CMOS technology

Semiconducting wafers

Photoresist processing

Field effect transistors

Overlay metrology

Scanning electron microscopy

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