A methodology is presented for optimizing transistor performance by considering the coupled response of the on- state and off-state parameters of saturated drain current and subthreshold drain leakage current, respectively. Good die yield in a CMOS digital logic integrated circuit is shown to be highly correlated to a multiple linear model of these transistor performance parameters using empirical data. These currents are correspondingly highly correlated to threshold voltage and effective channel length. Monte Carlo simulation is used to predict the distributions of saturated drain current and subthreshold drain current based on the natural variation of threshold voltage and effective channel length. A case study is presented using this methodology for the development of a CMOS retrograde well process using high energy implants from a baseline process using conventional diffused wells.