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27 August 1997 Prediction of CMOS transistor performance at 0.10-μm gate length using tuned simulations
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Abstract
Predictive device simulation is essential in order to improve MOSFET design, and reduce development time and costs. In this paper, the results of a simulation study carried out to predict the performance of N and P channel MOSFETs having a physical gate length of 0.10 micrometer at supply voltages of 1.2 and 1.5 V are presented. The study was used to determine the feasibility of the FOM goal for scaled 0.10 micrometer CMOS, and to identify the values of key device parameters [the external source drain resistance (Rext), poly-gate doping, etc.] which would improve device performance.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
S. Sridhar, Manoj Mehrotra, Mark Rodder, Mahalingam Nandakumar, and Ih-Chin Chen "Prediction of CMOS transistor performance at 0.10-μm gate length using tuned simulations", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); https://doi.org/10.1117/12.284594
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