27 August 1997 Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications
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Proceedings Volume 3212, Microelectronic Device Technology; (1997); doi: 10.1117/12.284616
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States
Abstract
In this paper, we discuss scaled silicon bipolar transistor performance for advanced BiCMOS SRAM applications. In particular, we present experimental results of non-self aligned, single poly emitter bipolar transistors with critical dimensions scaled vertically and laterally. We demonstrate the device performance enhancement by properly scaling and show device design tradeoffs with key bipolar device parameters.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
H. Tian, Asanga H. Perera, D. O'Meara, H. De, C. K. Subramanian, P. Rehmann, James D. Hayden, Norm Herr, "Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications", Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284616; https://doi.org/10.1117/12.284616
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KEYWORDS
Transistors

Doping

Silicon

Resistance

Capacitance

Boron

CMOS technology

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