Integration of low-k organic flowable SOG in a non-etchback/CMP process

George Chou; Amanda Shiaw-Rong Chen; W. Y. Hsieh

doi:10.1117/12.284654

5 September 1997 Integration of low-k organic flowable SOG in a non-etchback/CMP process

George Chou, Amanda Shiaw-Rong Chen, W. Y. Hsieh

Proceedings Volume 3214, Multilevel Interconnect Technology; (1997) https://doi.org/10.1117/12.284654
Event: Microelectronic Manufacturing, 1997, Austin, TX, United States

Abstract

As devices continuously shrink to deep sub-half micron, the requirements of multilevel interconnect technology become more stringent. A series of device experiments presented here evaluate the integration issues and electrical performance of both logic and SRAM chips fabricated using a low k spin-on material by a non-etchback process. Non-etchback processing is known for it's advantage of reduced cycle time and associated cost saving. Allied Signal's Accuspin 218, a flowable methylsilsesquioxane known for its stable dielectric constant of 2.7, is used throughout the study. Subsequent to SOG coating, several process modifications are implemented to enhance film uniformity and to reduce risks associated with via poisoning. These modifications include a non-conventional two-step baking sequence to enhance film uniformity and a vacuum cure in conjunction with an arsenic implant step to improve via resistance. CMP of the oxide deposited on top of SOG layer is used to provide the required global planarization. CVD tungsten plug process is chosen to test the SOG layer's ability to retain its low dielectric constant after exposure to high temperatures. To insure that photoresist and any polymeric residues are completely removed from the vias, device wafers are subjected to wet stripping and double oxygen plasma ashing. Electrical tests of 0.5 micrometers to 0.35 micrometers vias treated in this manner show that no via poisoning occurs anywhere in the devices. Reliability data from testing of 0.4 micrometers SRAMs is also satisfactory. These results suggest that this low k organic SOG non-etchback process, combined with CMP, is a viable IMD solution for 0.35 micrometers devices.

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George Chou, Amanda Shiaw-Rong Chen, and W. Y. Hsieh "Integration of low-k organic flowable SOG in a non-etchback/CMP process", Proc. SPIE 3214, Multilevel Interconnect Technology, (5 September 1997); https://doi.org/10.1117/12.284654

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KEYWORDS

Chemical mechanical planarization

Oxides

Tin

Dielectrics

Plasma enhanced chemical vapor deposition

Arsenic

Chemical vapor deposition

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