It will be demonstrated that the implementation of chemical mechanical polishing (CMP) for interlayer dielectric (ILD) planarization in a 0.5 micrometers CMOS-technology shows considerable productivity benefits compared to a planarizing resist etchback (PRE) process. Using a BPSG-ILD, the conventional resist etchback ILD-planarization with successive resist spin on and etch back showed high defect densities. These defects are related to the etchback- process. Particles dropping down from the chamber wall onto the wafer act as a mask for the etching process and cause steep, huge defects so called `mesa mountains'. Modifications of the etchback-process reduce the defect density, but there still remains some yield loss. By replacing the PRE sequence with CMP, the measured defect density could be significantly lowered resulting in a considerable yield gain of about 10% relatively. An additional advantage of CMP is the global planarization, which enhances the process window for contact and metal lithography. The smoother topography enables the lithography to reduce the exposure time and, by this, enhances throughput, in addition to the yield gain, a comparison of productivity relevant data show for the ILD-planarization sequence a clear advantage of CMP in cost (-30%) and (-40%).