Electrical defect density is simply a model or measurement of the number of electrical defects per unit area, which is a summation of yield loss from several sources, broadly classified into random and systematic failures. Random failure is typically from in-line defects (from equipment, process); systematic failure is from process marginality, parametric failure or design sensitivity. Assuming that after some amount of time systematic issues are mostly worked out, yield is then essentially defect limited, as is the case for most mature fabs/mature products running today. In this scenario, electrical defects density should hold to a predictable pattern dependent on minimum line width, process complexity and layout density (critical area). Understanding these relationships will greatly increase our ability to predict (defect limited) yield for new products at new technologies. The calculation of a critical area parameter, Ac, will be used in place of the area in electrical defect density calculations to obtain a critical area compensated DD that should be independent of device/design structure related effects. In addition, use of the critical area probability of fail curves will be used to estimate yield loss in-line and drive future defect improvements.