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11 September 1997 Modeling of defect propagation/growth for yield impact prediction in VLSI manufacturing
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Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material and the underlying IC topography. A rigorous topography simulator, METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy of this method which provided a framework for developing contamination to defect propagation/growth macromodels. We have demonstrated that the understanding of defect transformation can be applied to early yield impact prediction.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Xiaolei Li, Andrzej J. Strojwas, Aaron L. Swecker, Mahesh Reddy, Linda Milor, and YungTao Lin "Modeling of defect propagation/growth for yield impact prediction in VLSI manufacturing", Proc. SPIE 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III, (11 September 1997);

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