Translator Disclaimer
6 October 1997 Implementation of scheduling schemes using a sequencer circuit
Author Affiliations +
Proceedings Volume 3233, Broadband Networking Technologies; (1997) https://doi.org/10.1117/12.290470
Event: Voice, Video, and Data Communications, 1997, Dallas, TX, United States
Abstract
The implementation of different well-known scheduling schemes using a cell sequencer/scheduler circuit, already proposed by the authors, is investigated. Two groups of scheduling schemes, namely priority-based and rate-based schemes are considered. The first group includes static and dynamic priority schemes such as head-of-line priority and windowed priority schemes. The second group includes fair queueing, self-clocked fair queueing, and pacing mechanisms. The application of the sequencer in shaping and policing circuits in ATM networks is also addressed. A mechanism of scheduling real-time and non-real-time traffics using two different algorithms but a common sequencer is also presented to demonstrate the capability of the sequencer to implement a combination of algorithms and functions in the same environment.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Massoud R. Hashemi and Alberto Leon-Garcia "Implementation of scheduling schemes using a sequencer circuit", Proc. SPIE 3233, Broadband Networking Technologies, (6 October 1997); https://doi.org/10.1117/12.290470
PROCEEDINGS
10 PAGES


SHARE
Advertisement
Advertisement
RELATED CONTENT


Back to Top