Translator Disclaimer
12 February 1997 OPC technology road map to 0.14-μm design rules
Author Affiliations +
We devised an OPC technology roadmap (Table 1) embodied in a corresponding test reticle (code named RTP4) as a benchmark for the reticle manufacturing industry. This reticle includes the polysilicon gate layer of four large ASIC-style microprocessor chips, representing four design rule generations: 0.25 micrometer, 0.20 micrometer, 0.18 micrometer, and 0.14 micrometer. In this report we summarize the challenges experienced during the building of this reticle, beginning with the scaling of scattering bar and serif OPC features according to exposure wavelength and numerical aperture. CAD data handling issues such as overall pattern complexity and choice of grid size are discussed. Three out of four RTP4 reticles made by Photronics (all written by a MEBES 4500 tool) were shown to have acceptable pattern quality. Successful die-to-database inspections for all four primary chips on one of the RTP4 reticles were performed by Applied-Orbot using their RT-8000 and RT-8000-ES systems. We also offer an initial look at the performance of this OPC technology on printed wafers with 0.18 micrometer and 0.14 micrometer line features.
© (1997) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
J. Fung Chen, Thomas L. Laidig, Kurt E. Wampler, Roger F. Caldwell, Alex R. Naderi, and Douglas J. Van Den Broeke "OPC technology road map to 0.14-μm design rules", Proc. SPIE 3236, 17th Annual BACUS Symposium on Photomask Technology and Management, (12 February 1997);

Back to Top