23 April 1998 Electron/hole velocity overshoot in sub-100-nm Si metal-oxide-semiconductor field-effect transistors and its application to low-voltage operation
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Abstract
We have experimentally studied the electron velocity overshoot and the mechanism of its degradation in the inversion layer of sub-100 nm metal-oxide-silicon field-effect-transistors (MOSFETs). Both silicon-on-insulator (SOI) and bulk structures were studied. At low transverse electric fields, that is, for low carrier densities in SOI devices under low gate drive conditions, it is possible to achieve electron velocity overshoot due to non-stationary transport in the sub-100 nm region. However, it is very difficult in MOS structures to improve electron velocity at high surface electron densities, because of the reduced electron mobility in high transverse fields. Moreover, the surface electron density of MOS structures is reduced when a low channel impurity concentration is chosen to improve low field mobility; this results from the expanded inversion layer width. These results indicate the physical limitations of scaled MOS structures as regards the realization of higher current capabilities. According to both the above discussion and the statistical performance fluctuation data, we introduce a new scaling scenario for sub-100 nm SOI devices and show its possibility for high current drivability and suppressed performance fluctuation in sub-100 nm ultra-large-scale-integrations (ULSIs).
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Tomohisa Mizuno, "Electron/hole velocity overshoot in sub-100-nm Si metal-oxide-semiconductor field-effect transistors and its application to low-voltage operation", Proc. SPIE 3277, Ultrafast Phenomena in Semiconductors II, (23 April 1998); doi: 10.1117/12.306151; https://doi.org/10.1117/12.306151
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