1 April 1998 Time delay and integration image sensor with high-speed output architecture
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Abstract
Today's imaging systems utilize fast operation to increase their throughput. At high line rates the illumination required to collect a reasonable image becomes prohibitive. Time delay and integration (TDI) offers greatly enhanced responsivity to allow faster operation in terms of line rates. This combination of sensitivity and speed is unmatched in other sensor architectures. The standard multi- stage source follower output amplifier usually involves a trade off between speed and sensitivity through sizing of the first FET. We present a high bandwidth and sensitivity, scalable architecture for readout of TDI sensors. A key component of this architecture is the minimization of output amplifier load and parasitic capacitance. The methodologies used in the design and modeling of the output structure will be presented. This basic model has been confirmed over a range of device dimensions. A 4096 element, multi-tap TDI image sensor incorporating this architecture has been fabricated using a standard CCD process. Discrete and in- camera measurements will be presented demonstrating operation at > 100 kHz line rates and with > 300 V/((mu) J/cm2) peak responsivity. Methods of controlling and reducing the stray loading on the sensor output will also be discussed.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gareth P. Weale, Gareth P. Weale, Colin J. Flood, Colin J. Flood, Douglas R. Dykaar, Douglas R. Dykaar, } "Time delay and integration image sensor with high-speed output architecture", Proc. SPIE 3301, Solid State Sensor Arrays: Development and Applications II, (1 April 1998); doi: 10.1117/12.304559; https://doi.org/10.1117/12.304559
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